Category: Embedded Diagnostics

Highly Accelerated Life Testing (HALT) and Highly Accelerated Stress Screening (HASS) are often used to detect faults in electronic systems, testing the extremes and determining the outer limits of system margins. All hardware components and systems will eventually fail under environmental stress. But can this technique be used to improve software reliability as well?
Last month, we saw how defects on memory data lines can cause a system to fail, and yet escape detection by the system boot loader or BIOS. Let’s examine this in more technical detail.
Embedded run-control (aka on-chip debug, or processor debug port control) has numerous benefits in the areas of test and debug, for Design Engineering, Manufacturing Test Engineering, and Field Service. What are they?
Board bring-up is a phased process whereby an electronics system is repeatedly tested, validated and debugged, in order to achieve readiness for manufacture. This process can take so long that a product never gets to market because it is succeeded by the next generation...
I was reflecting on how much processor speeds, memory, and data transmission rates have increased over the last few decades. And yet the same old tools and techniques are often used to bring up new designs. When do you think we fall off the cliff?
The challenge of system debug on Intel (and other) systems can be huge. What new tricks are available for debugging system hangs, crashes, or application errors?
Is your laptop highly available? Maybe not yet, but... The author ruminates on why he's spending his precious weekend hours troubleshooting gadgets that should work all the time.
ScanWorks Embedded Diagnostics is embedded firmware which uses a CPU’s debug port to access a system’s architecturally visible registers, memory and I/O. See the technology and benefits behind this "debugger on steroids".
ScanWorks Embedded Diagnostics for x86 systems requires a connection between the embedded service processor (BMC, FPGA or other) supporting run control and the target CPU(s). The nature of these connections is described herein.
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