Boundary Scan Archives | Page 11 of 13

Structural Defects on High-Speed Serial I/O – Part 3

Alan Sguigna

March 31, 2013
1:51 pm

In the first two parts of this multi-part blog, we reviewed different kinds of short circuit, open circuit, and stuck-at faults and how they might affect link performance. Let’s recap and rank these defects and see what we can do about them.

IEEE 1149.7 JTAG Tutorial | eBook

Arden Bjerkeli

March 21, 2013
6:12 pm

Testing Intel Sandy Bridge and Ivy Bridge

Alan Sguigna

September 30, 2012
2:24 pm

In my last few blogs, I’ve talked about the challenges of testing QPI, PCI Express, SATA 3, and DDR3 memory. These buses are common to many Intel Sandy Bridge and Ivy Bridge motherboard designs. Should test engineers take chances and just not test them?

Problems with Powered Opens on ICT

Alan Sguigna

September 16, 2012
1:45 pm

If you’re using Powered Opens on In-Circuit Test, you may not be getting the test coverage you expect.

Testing SATA 3

Alan Sguigna

September 9, 2012
2:27 pm

Serial ATA 3 (SATA 3, or SATA III) is a differential bus running at 6Gbps. It’s commonly used on computer motherboards, such as notebooks, to connect to mass storage devices. How do you know if your hard disk or flash drive is running at full speed?

Testing Intel QuickPath Interconnect

Alan Sguigna

August 26, 2012
3:11 pm

Last week I published a blog on detecting defects on PCI Express. Does Intel QuickPath Interconnect (QPI) differ in any way?

Testing PCI Express

Alan Sguigna

August 16, 2012
8:16 pm

PCI Express (PCIe) buses, in particularly Gen3, are susceptible to defects which may be masked from conventional test. What are these defects and how are they detected?

How to test DDR3, DDR4 and other memory buses is top-of-mind for many engineers. And rightfully so.

Alan Sguigna

July 25, 2012
2:55 pm

Testing high-speed memories soldered to a circuit board is as elusive as it is critical for overall system performance. Testing DDR3 and DDR4 memory buses can be particularly tricky, given the fact that DDR is so fast and that the bus carries the clock and data on both the rising and falling edges of the signal. Sorting all of that out and making sure it stays sorted out over the life cycle of a system can be a daunting challenge.

You, our users, show us the full potential of new boundary-scan test tools

Kent Zetterberg

July 2, 2012
10:53 am

The Limitations of Boundary Scan on ICT

Alan Sguigna

May 28, 2012
4:12 pm

Many legacy In-Circuit Testers (ICT) support some kind of boundary scan for structural testing, to address limited access issues. But are these as good as advertised?

Category: Boundary Scan

Structural Defects on High-Speed Serial I/O – Part 3

IEEE 1149.7 JTAG Tutorial | eBook

Testing Intel Sandy Bridge and Ivy Bridge

Problems with Powered Opens on ICT

Testing SATA 3

Testing Intel QuickPath Interconnect

Testing PCI Express

How to test DDR3, DDR4 and other memory buses is top-of-mind for many engineers. And rightfully so.

You, our users, show us the full potential of new boundary-scan test tools

The Limitations of Boundary Scan on ICT

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