Category: Industry Standards and Forums

PCI Express 4.0, Retimers, and Trace Length

Alan Sguigna

June 15, 2014
4:39 pm

At their developers conference two weeks ago, PCI-SIG representatives talked about doubling the bandwidth of PCI Express 3.0, while still preserving channel runs of up to 20 inches, the length of the traditional server’s data path. How is this achieved?

Will BIST Kill T&M?

Alan Sguigna

September 29, 2013
5:14 pm

To quote Ransom Stephens in the DesignCon Community Blog, “BIST (Built-In System Test), is an acronym that would keep executives at test-and-measurement companies awake at night, if they knew what it meant.” What’s he talking about?

First to support all of Intel® Silicon View Technology

Eric Johnson

June 10, 2013
9:19 am

Signal Integrity testing with CRCs versus pattern generation and capture

Alan Sguigna

January 9, 2013
4:45 pm

I was asked recently whether engineers could just check the CRC error counts coming from the Operating System to ensure they had good signal integrity and operating margins. After all, a CRC checks for bit errors, right? Here’s why this is not good enough:

Diminishing ICT Test Coverage

Alan Sguigna

December 31, 2012
4:28 pm

Our chief technologist of non-intrusive board test, Adam Ley, recently published an e-Book on solving the problem of diminishing test coverage from In-Circuit Test (ICT). What’s the key take-away from this publication?

Problems with Powered Opens on ICT

Alan Sguigna

September 16, 2012
1:45 pm

If you’re using Powered Opens on In-Circuit Test, you may not be getting the test coverage you expect.

Is there a market for on-chip instrumentation?

Alan Sguigna

September 3, 2012
1:42 pm

Brian Bailey, editor of EETimes’ EDA Designline, recently penned a blog questioning the ubiquity and value of embedded instrumentation within chips. It’s a fascinating and timely read, and I’d like to put my two cents worth in…

Testing PCI Express

Alan Sguigna

August 16, 2012
8:16 pm

PCI Express (PCIe) buses, in particularly Gen3, are susceptible to defects which may be masked from conventional test. What are these defects and how are they detected?

Testing DDR3 and DDR4 memory – Part 2

Alan Sguigna

August 3, 2012
4:52 pm

In my last Blog, I wrote about the iNEMI report on how testing memories is one of the top three problems engineers face today. Why is memory test so important?

The Limitations of Boundary Scan on ICT

Alan Sguigna

May 28, 2012
4:12 pm

Many legacy In-Circuit Testers (ICT) support some kind of boundary scan for structural testing, to address limited access issues. But are these as good as advertised?

Category: Industry Standards and Forums

PCI Express 4.0, Retimers, and Trace Length

Will BIST Kill T&M?

First to support all of Intel® Silicon View Technology

Signal Integrity testing with CRCs versus pattern generation and capture

Diminishing ICT Test Coverage

Problems with Powered Opens on ICT

Is there a market for on-chip instrumentation?

Testing PCI Express

Testing DDR3 and DDR4 memory – Part 2

The Limitations of Boundary Scan on ICT

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