Category: Software Debug and Trace – Intel

In my last article, I described how the Open Compute Project (OCP) Project Olympus server designs have been put into the public domain by Microsoft Azure. Inherent in the Olympus servers is the hardware connection between the ASPEED BMC and the CPU JTAG chain. To make the most of this connection for hardware-assisted debug and test purposes, a high-performance, secure JTAG Master function is needed within the BMC.
As part of the Open Compute Project, Microsoft Azure is leading the charge in providing the technical information needed to democratize the server industry. Recently, they put into the public domain the full schematics and board files for an Intel Xeon Scalable Processor (Skylake-EP) server design. Reviewing the schematics provides great insight into the hardware design implementation needed to support at-scale debug via embedded JTAG run-control.
In Episode 24, I finished off my new build machine, successfully did a QEMU image build on it, and loaded an off-the-shelf Ubuntu image into my new MinnowBoard Turbot. This week, I tackled a MinnowBoard Linux image build using Yocto, loaded it into my MinnowBoard, and also set about doing a Yocto image build for the Portwell Neptune Alpha board. But I ran into some problems.
Intel® has announced the new family of 8th Gen Intel Core desktop processors, available for purchase beginning October 5, 2017. ASSET's SourcePoint has supported the 8th Gen (codenamed Coffee Lake) since earliest silicon.
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