Processor-Controlled Test (PCT) Archives | Page 2 of 5

Frost & Sullivan recognizes the user value of SourcePoint and ScanWorks

Glenn Woppman

December 9, 2014
11:30 am

Memory Training, Testing, and Margining

Alan Sguigna

November 2, 2014
3:38 pm

What happens during DDR memory training/initialization, and how does it differ from what is needed for manufacturing testing or system marginality validation?

JTAG | one TAP, many non-intrusive apps

Adam Ley

September 9, 2014
12:42 pm

The origins of JTAG are inextricably bound up with boundary scan. Yet, it provides many capabilities to many purposes. Often, as part of a point tool, whether for debug, programming, test or validation, it takes on just one capability. But, no matter the purpose, as the thread common to all, the standard Test Access Port (TAP) opens the way for many applications. In the test domain, several of these unite under the banner Non-intrusive Board Test (NBT).

Embedded ITP for Remote Debug

Alan Sguigna

July 24, 2014
3:30 pm

A leading server OEM is using an embedded implementation of Intel In-Target Probe (ITP) to perform at-scale debugging, without plugging in an external emulator. How does this work?

DDR Testing using Spoofed Memory Reference Code – Part 2

Alan Sguigna

July 20, 2014
3:42 pm

In Part 1 of this blog, we discussed some of the limitations of ICT, boundary-scan, and conventional functional test for testing memories. This Part 2 reviews methodologies that overcome these constraints.

DDR Testing using Spoofed Memory Reference Code – Part 1

Alan Sguigna

July 13, 2014
2:55 pm

Off-the-shelf memory initialization routines typically do not provide the needed diagnostic resolution if a structural failure causes the system to “blue screen”. How can test engineers overcome this?

What is Board Bring-Up – Part 2

Alan Sguigna

March 9, 2014
4:09 pm

We know that the board bring-up process can be extremely challenging on today’s complex, high-speed designs. How do we get the iterative validation, test and debug steps off of the critical path of new product introduction?

Debugging Dead Boards in Production

Alan Sguigna

December 7, 2013
3:04 pm

A Case Study showed that 50% of circuit boards that tested as “dead” in manufacturing production actually have defects on their memory buses. What categories of memory interconnect defects cause a dead board?

Will BIST Kill T&M?

Alan Sguigna

September 29, 2013
5:14 pm

To quote Ransom Stephens in the DesignCon Community Blog, “BIST (Built-In System Test), is an acronym that would keep executives at test-and-measurement companies awake at night, if they knew what it meant.” What’s he talking about?

Boundary-Scan Testing of DDR3 and DDR4 Memory

Alan Sguigna

July 13, 2013
4:52 pm

In the blog Boundary-Scan Testing of PCI Express, we examined how JTAG can be used to detect structural defects on high-speed serial I/O. Now let’s review the situation for DDR3 and DDR4 memory.

Category: Processor-Controlled Test (PCT)

Frost & Sullivan recognizes the user value of SourcePoint and ScanWorks

Memory Training, Testing, and Margining

JTAG | one TAP, many non-intrusive apps

Embedded ITP for Remote Debug

DDR Testing using Spoofed Memory Reference Code – Part 2

DDR Testing using Spoofed Memory Reference Code – Part 1

What is Board Bring-Up – Part 2

Debugging Dead Boards in Production

Will BIST Kill T&M?

Boundary-Scan Testing of DDR3 and DDR4 Memory

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