It is often part of a hardware validation test suite to initiate multiple PCIe bus retrains, looking for hardware design issues, or LTSSM RTL bugs in the device under test. These test suites take a very long time to run. Is there a way to speed them up?
ASSET joined the Open Compute Project (OCP) earlier this year, and we attended our first Engineering Workshop in Dallas last week. The theme of this session was the OCP Telco Project. What did we learn?
Intel Processor Trace (Intel PT) is a capability on new Intel silicon that captures information about software execution using dedicated hardware facilities inside the chip. How is it used to debug UEFI?
Heterogeneous Computing refers to systems that use more than one kind of processor, typically a combination of CPUs and GPUs, sometimes on the same silicon die. Is this solution optimized for supercomputing applications?