SourcePoint AMD Help

Table of Contents


Display or change how command line memory accesses use cached memory.


cachememory [= bool-cond]



specifies a number or an expression that must evaluate to true (non-zero) or false (zero).


Use the cachememory control variable to control how SourcePoint handles command line memory accesses. The default setting for cachememory is false. Entering the control variable without an option displays the current setting.

When SourcePoint reads target memory, it normally reads blocks of 128 bytes at a time. This minimizes the time it takes for refreshing Code and Memory windows. The data read is cached in SourcePoint. Whenever a go or step operation is performed, this cache is cleared.

The Command window is an exception, however. Whenever a command is executed that results in a memory access (asm, ord1, ord2, ord4, etc.), SourcePoint always reads from target memory, even if it already has the data in its cache. It also reads only the amount of data requested (e.g., an ord4 command reads exactly four bytes). This is so that accesses to memory-mapped I/O work properly.

There are times, however, primarily when executing command files that perform numerous memory accesses, where it is preferable to use the block-read, cached-memory approach. That is the purpose of the cachememory control variable. When false, the Command window reads and writes only the number of bytes specified and does not cache data read. When true, the Command window reads memory in blocks and caches the data read. Command files that perform a number of memory operations run much faster when cachememory is set to true.

Example 1

Command input:

cachememory           // display the current setting



Example 2

Command input:

cachememory = true    // enable block memory reads and caching

ord4 100              // cachememory is true, only one target

                      // memory read at 100-17f will occur

ord4 10

ord4 108

Example 3

Command input:

cachememory = false   // disable block memory reads and caching

ord4 100              // cachememory is false, three separate

                      // target memory reads will occur

ord4 10

ord4 108