JTAG/boundary-scan test can be embedded as firmware within a PCB’s service processor. This guide describes the related JTAG technology and its implementation. Become an expert in this innovative application of IEEE 1149.1!

The ability to thoroughly test, characterize and diagnose faults and failures with soldered-down memory is one of the most pressing problems in the industry. With ASSET InterTech’s ScanWorks® Boundary-Scan Test, engineers designing with Double Data Rate 4 (DDR4) memory devices can facilitate shorts and opens testing on control, address, and data lines.

This guide will take the reader step by step through the setup and testing of the Xilinx Zynq UltraScale+ UltraZed target using the ScanWorks® PFx products. The ScanWorks PFx products include three distinct tools focus at design and test engineering production challenge when dealing with DDR test, fast flash programming and circuit board test. It is said that a picture is worth a thousand words. When investigating solutions for new design, a user guide can provide a picture that can bring additional clarity. This guide shows how to test DDR memories, functionally test the circuit board without a bootloader or OS, and program flash at device speeds. All this capability is driven by the SoC because of next generation embedded IP provided by ASSET.

Embedded software tuning on an SoC for DDR memories is the next evolution in technology and it is available today. The technology should not only provide the ability for automatic DDR calibration optimization but allow interactive tuning adjustments. The interactive adjustments are necessary to handle component changes, environmental impacts, and engineering experiments in support of the designer as they ensure optimum settings for the DDR memory controller and PHY in their designs.

Embedded software tuning on a SoC for DDR memories is the next evolution in technology and it is available today. The technology should not only provide the ability for automatic DDR calibration optimization, but allow interactive tuning adjustments. The interactive adjustments are necessary to handle component changes, environmental impacts, and engineering experiments in support of the designer as they ensure optimum settings for the DDR memory controller and PHY in their designs. The technology must be backed up with strong memory test infrastructure from structural-to-functional. The functional test must include memory traffic generation which includes noise injection.  Without a strong memory test suite, it is not possible to verify the performance that results from the register value changes that control the memory transactions from SoC-to memory components.

This guide will take the reader step by step through the setup and testing of the SABRE Lite board using the ScanWorks PFx products. The ScanWorks PFx products include three distinct tools focus at design and test engineering production challenge when dealing with DDR tuning and test, fast flash programming and circuit board test. The reader will get a true sense of how easy it is to calibrate or tune and test DDR memory. Or run a processor based functional test on the SABRE Lite board to test the Ethernet Phy or other devices on the multiple IO buses provided on the NXP i.MX6 SoC. Or program the MMC via Ethernet. No marketing fluff here just bare fact on the user development process and ease of use.

This guide will take the reader step by step through the setup and testing of the Xilinx Zynq-7000 ZedBoard using the ScanWorks PFx products. The ScanWorks PFx products include three distinct tools focused on design and test engineering production challenges when dealing with DDR tuning and test, fast flash programming and circuit board test. It is said that a picture is worth a thousand words. When investigating solutions for new design, a user guide can provide a picture that can bring additional clarity. This guide shows how to tune or test DDR memories, functionally test the circuit board without a bootloader or OS, and program flash at device speeds. All this capability is driven by the SoC using next generation embedded IP provided by ASSET.

PXIe-based test systems fill an important role in satisfying functional ATE test requirements for digital, analog, and RF interfaces on defense and avionics applications. Teradyne’s PXIe-based High Speed Subsystem (HSSub) has become the industry standard for PXIe-based test systems for defense and avionics applications. Through a collaborative development effort, ASSET’s ScanWorks Boundary Scan Test software can be installed and run on the HSSub. Making Boundary Scan test vectors available through the HSSub increases diagnostic test capabilities, while reducing test cost and test times significantly over the entire life cycle of a product for new and existing HSSub users.