This eBook will chronicle our own experiences with dealing with these problems and use a Commercial Off the Shelf (COTS) board to delve deeply into the testing. We will emphasize the testing of DDR memory both structurally and functionally.  A Design For Test (DFT) analysis of the target board starting with the System on Module (SOM) and continuing with the Carrier Card (CC) will be described.
Download this e-book and learn all there is to know of about the boundary scan JTAG (TAP) architecture and the problems it solves to create high test coverage.  Written by Dr. Ben Bennetts, a leading Design For Testability (DFT) expert who has worked for GenRad, Synopsys and LogicVision. Additional content has been added to this e-book by ASSET’s own Chief Technology Officer Adam Ley and Application Engineer Ben Bales.
As this eBook enters its 3rd edition, content has been added describing some of the latest advancements in DDR memory, power, speed, and test technology. New memory devices such as DDR5 which utilize CT mode, and Graphics Double Data Rate 5 (GDDR5) SDRAM and GDDR6 Synchronous Graphics Random Access Memory (SGRAM) devices that implement forms of boundary-scan test technology, are described herein.

ScanWorks users can bridge the coverage gap between boundary scan and functional test via its Component action. This action allows for testing of non-boundary scan devices, such as analog to digital converters (ADCs), digital to analog converters (DACs), Ethernet PHYs, LED, switches, clocks, and other non-boundary scan devices through the PCBs boundary scan infrastructure.

This eBook describes how to create a ScanWorks FPGA-based Flash Programming project. Using the Opal Kelly XEM6002 board equipped with a Xilinx Spartan-6 FPGA as an example, we go step-by-step through everything necessary to prepare and run super-speed programming of the attached SPI flash devices. The results are dramatic improvement in programming speed over traditional JTAG/boundary scan.

JTAG/boundary-scan test can be embedded as firmware within a PCB’s service processor. This guide describes the related JTAG technology and its implementation. Become an expert in this innovative application of IEEE 1149.1!

The ability to thoroughly test, characterize and diagnose faults and failures with soldered-down memory is one of the most pressing problems in the industry. With ASSET InterTech’s ScanWorks® Boundary-Scan Test, engineers designing with Double Data Rate 4 (DDR4) memory devices can facilitate shorts and opens testing on control, address, and data lines.

This guide will take the reader step by step through the setup and testing of the Xilinx Zynq UltraScale+ UltraZed target using the ScanWorks® PFx products. The ScanWorks PFx products include three distinct tools focus at design and test engineering production challenge when dealing with DDR test, fast flash programming and circuit board test. It is said that a picture is worth a thousand words. When investigating solutions for new design, a user guide can provide a picture that can bring additional clarity. This guide shows how to test DDR memories, functionally test the circuit board without a bootloader or OS, and program flash at device speeds. All this capability is driven by the SoC because of next generation embedded IP provided by ASSET.