Testing platforms designed with Intel® Architectures (IA) can be extremely difficult and testing memories near impossible. If you are still using a production BIOS to configure your memory subsystem during manufacturing test, you may be missing issues that are an artifact of how the BIOS configures the memories.
With tremendous growth in capacity, programming NOR and NAND flash memories at full functional speed is a must. But how? Here are the ins and outs on using an onboard FPGA and IJTAG, the IEEE 1687 Internal JTAG standard.
What happens when you’re mixing multiple embedded TAPs – eTAPs? Like when TAPs for IEEE 1149.1 boundary scan, JTAG software debug ports (ARM DAP, Intel ITP) and IJTAG instruments are all in the same SoC design? You might be in for an ugly surprise. The eTAPs accessed through the chip-level TAP might not do what you had in mind.
For circuit board manufacturers, a self-healing bus like Intel® QPI can be self-defeating. Especially when it comes to board quality and diagnosing structural defects. Functional tests will typically not detect QPI faults like shorts and opens because they can be hidden by QPI’s self-repairing capabilities. Often, QPI buses with structural faults will train up well enough to slip through functional testing, only to manifest user problems later like reduced performance, more lane drop-outs, hangs and others.
A circuit board doesn’t have to be operational for functional tests to be applied to its I2C (Inter-Integrated Circuit) interfaces. What you need is 3 things: on-board 1149.1 JTAG, an FPGA and some IP. In fact, the board doesn’t even have to boot and its functional firmware/software can be a long way from complete. Now, that’s powerful.
Without security, what do we expect the hackers to do? Face the facts: There are no industry standards for semiconductor and board test security. None in the JTAG and IJTAG standards. So all the board/system developers can do is integrate a variety of different semiconductor security protocols. But some chips have no test security at all!
In-system programming (ISP) of memories within the manufacturing flow is well established. However, the industry has taken a step backward to off-line device programming because the increasing size of flash memory has lengthened programming times with legacy methods.
How do you verify the hardware functionality of serial communication interfaces on a new board, such as UART, SPI, I2C, before the system’s functional software has been completed? The answer is: you can’t.
Boards and chips keep getting denser, faster. And the speed is higher so they’re a whole lot more sensitive. Slight variances or defects cause intermittent crashes and performance degradation. And the negative effects interact. Welcome to living “on the edge.”
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