Memory Fault Insertion and Detection of Intel 4th Generation Core Family

In the paper, faults are inserted on an Intel® Shark Bay platform, and the ScanWorks® Processor-Controlled Test product is used to detect a myriad of faults. Real life examples always provide for more clarity as shown in this paper. 

Time is of the essence when dealing with memory issues on Intel® Architectures (IA) like Haswell, whether during board bring-up or manufacturing. To shorten production or development time in dealing with memory test problems, a tool that provides robust diagnostics is crucial. The diagnostic information needs to be bit specific, whether working with solder down memories or DIMMs.

There are two distinct stages, when dealing with memory testing, where a problem may surface. These two stages are the memory setup and the actual memory test. The memory setup is often an overlooked element of the problem. For Intel, the memory setup is buried within the BIOS and depending on how the BIOS is written, may obfuscate some problems during the test.


  • Diagnostic resolution to increase yield
  • Solving the complex memory test problem
  • Save time finding shorts and opens
  • Understanding bit swizzling impact on test
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