Real Insight from Code to Silicon
Platform for Software Debug and Trace
Platform for Embedded Instruments
More Visibility Where It Counts
As this eBook enters its 3rd edition, content has been added describing some of the latest advancements in DDR memory, power, speed, and test technology. New memory devices such as DDR5 which utilize CT mode, and Graphics Double Data Rate 5 (GDDR5) SDRAM and GDDR6 Synchronous Graphics Random Access Memory (SGRAM) devices that implement forms of boundary-scan test technology, are described herein.
Latest Articles & Press Releases
Hypervisor and OS Kernel Debug with DCI on the AAEON Whiskey Lake board
DCI debug of UEFI and hypervisor technologies with full source code.
Advanced Breakpoints for AMD Debug
It’s probably not well-known, but AMD platforms have special low-level breakpoint capabilities that aren’t available on Intel platforms. They are extremely powerful; here’s how to use them.
JTAG Debug using DCI on the AAEON UP Xtreme Whiskey Lake board
If you want to learn about UEFI, you have to be able to see the source code and debug it. Here’s how to build a debug Tianocore image on the AAEON UP Xtreme Whiskey Lake board, flash it onto the target, and use SourcePoint to debug it with Intel Direct Connect Interface (DCI).
Using JTAG for Hypervisor Debug: Part 3
Using a JTAG-based debugger to do Type 1 UEFI hypervisor debug.
Learn More Live
Here’s your chance to see how easy it is to debug and test using SourcePoint or ScanWorks. Let us walk you through it!