Real Insight from Code to Silicon

Platform for Software Debug and Trace

Platform for Embedded Instruments

Software Debug

All the tools you need to debug and trace ARM and Intel embedded applications in one place.

Hardware Validation

Quickly validate both hardware/firmware interactions and operating margins in our design.

Chip Debug

All the tools you need to debug and trace ARM and Intel embedded applications in one place.

Manufacturing Test

Non-intrusive test technologies to maximize test coverage and diagnostics.

Testing DDR4 memory with Boundary Scan/JTAG

The ability to thoroughly test, characterize and diagnose faults and failures with soldered-down memory is one of the most pressing problems in the industry. With ASSET InterTech’s ScanWorks® Boundary-Scan Test, engineers designing with Double Data Rate 4 (DDR4) memory devices can facilitate shorts and opens testing on control, address, and data lines.

UEFI Framework Debugging | SourcePoint - Updated Version, November 2018!!

Accelerate your Xilinx Zynq UltraScale+ designs with PFx

Cut DDR tuning and test development efforts in half on i.MX 6-based designs

Webinar: JTAG-based debugging of AMD EPYC servers

January 5, 2021

ASSET is pleased to announce that yours truly is presenting a technical session on JTAG-based firmware debugging of AMD EPYC servers, to be held on Wednesday, January 27th at 1:30pm Central Standard Time.

The UP Squared Chronicles Episode 4: Using Intel Processor Trace with POST Codes

January 3, 2021

I became curious this past week on how UEFI handles POST codes. These are “markers” for the boot process, and tells you at what stage the platform initialization is. Can we easily correlate POST codes with the operation of the UEFI firmware?

The UP Squared Chronicles Episode 3: Intel Processor Trace

December 21, 2020

Wow! It has been a while. I wrote Episode 2 of my open-source explorations into the AAEON Intel Apollo Lake-based Up Squared board back on June 7th. In that episode, I gave directions on how to build the UEFI debug image for the board, complete with source/symbols for consumption by JTAG debuggers like SourcePoint. In this episode, I show source-level debug with SourcePoint, and take advantage of Intel Processor Trace on the board.

Video recording of Chiplet interconnect test webinar

December 3, 2020

In case you missed it, a recording of Michael Johnson's webinar, Chiplet Interconnect Testing using JTAG/Boundary Scan, is now available. Click on the link, and enjoy the show.

Learn More Live

Here’s your chance to see how easy it is to debug and test using SourcePoint or ScanWorks. Let us walk you through it!