Real Insight from Code to Silicon

Platform for Software Debug and Trace

Platform for Embedded Instruments

Software Debug

All the tools you need to debug and trace Intel, AMD and Arm embedded applications in one place.

Hardware Validation

Quickly validate both hardware/firmware interactions and operating margins in our design.

Chip Debug

Verify, test and characterize SoCs, FPGAs and ASICs pre- and post-tapeout.

Manufacturing Test

Non-intrusive test technologies to maximize test coverage and diagnostics.

Guidelines for System-level JTAG Design

System-level JTAG, or SJTAG, expands the application potential of JTAG significantly beyond the traditional board-level scope of structural tests. System-level JTAG is well-suited for functional tests, device programming, and in-situ diagnostics.

Guidelines for Board Design for Test (DFT) based on Boundary Scan – Volume 2

Guidelines for Board Design for Test (DFT) based on Boundary Scan – Volume 1

DDR Memory Test: Modern Tools for validation, Test, and Debug

The US CHIPS Act 1+ Year Later – Things are Happening!

November 8, 2023

Structures have been put in place. There is a commitment to funding. Strategies are being established. In this blog I cover some of the things that have happened since the passage of the CHIPS and Science Act in August last year.

Everything You Need to Know About ScanWorks Interconnect Part 12 – Working with a Netlist (Cont’d.)

November 8, 2023

Using the Device Browser to specify cluster, dummy, and resistor models for non-Boundary Scan devices on our board. This blog is a continuation of Part 11, "Everything You Need to Know About ScanWorks Interconnect – Working with a Netlist".

Everything You Need to Know About ScanWorks Interconnect Part 11 – Working with a Netlist

October 31, 2023

Before we can test our device-to-device interconnects with an Interconnect action, we need to complete the Describe Design step. In this blog post we discuss working with netlists.

Silent Data Corruption: A Survey Article

October 29, 2023

The topic of Silent Data Corruption (SDC) is very hot; in short, SDC is a result of flaws within a semiconductor that causes invisible errors in the data that it processes. As one example of this, a CPU might erroneously calculate 1+1 and yield 3.

Learn More Live

Here’s your chance to see how easy it is to debug and test using SourcePoint or ScanWorks. Let us walk you through it!