Guidelines for System-level JTAG Design

When boards are assembled into a system, faults can arise, even with boards that have been previously tested with JTAG. System-level JTAG, or SJTAG, significantly expands the application potential of JTAG beyond the traditional board-level scope of structural tests. With proper application, JTAG is perfectly suited to detect faults between boards that have been assembled in a system. SJTAG is well-suited for functional tests, device programming, and in-situ diagnostics.

System-level JTAG design guidelines must be followed to ensure access to individual boards that comprise the system. There are several design architectures for system-level JTAG. Each design architecture has advantages and disadvantages. There are also multi-drop devices and multi-TAP hardware that can be used to implement a system-level JTAG design.

The guidelines for system-level JTAG design presented in this eBook (part 3 in our Design for Test eBook series) have been assembled over many years of experience by the technical staff of ASSET InterTech, Inc.

This eBook builds upon the guidelines for board design for DFT based on Boundary Scan presented in Volumes 1 and 2, but now expanding JTAG to the system level.

Guidelines for System-level JTAG Design highlights:

  • System-level JTAG design architectures
  • Multi-drop devices used to implement system-level JTAG
  • Multi-TAP hardware used to implement system-level JTAG
  • Embedded applications used to implement system-level JTAG