Guidelines for Board Design for Test (DFT) based on Boundary Scan – Volume 2
As PCBs move through the manufacturing process, the goal is to reduce the number of defective PCBs produced. Structural defects need to be identified quickly so they can be repaired, and processes can be adjusted. Following guidelines for board design for test (DFT) based on Boundary Scan ensures printed circuit board (PCB) test coverage is maximized. Boundary Scan can also be used for structural tests of memory devices, to configure field programmable gate array logic (FPGA) devices, and to program various types of flash memory devices.
The Boundary Scan DFT guidelines in this eBook have been assembled over many years of experience by the technical staff of ASSET InterTech, Inc. Building on the guidelines presented in Volume 1, this eBook focuses on structural memory tests, flash programming, and FPGA configuration.
Volume 2 highlights:
- Increasing interconnect test coverage with Cluster Models
- Controlling clock sources to reduce possible noise
- Eliminate bus contention during memory interconnect testing
- Decrease flash programming time with external configuration options
- Boundary Scan testing with unconfigured or configured FPGAs
