Guidelines for Board Design for Test (DFT) based on Boundary Scan

Implementing boundary scan Design for Test (DFT) guidelines adds the unique capability of accessing onboard boundary scan test resources for a non-intrusive test which provides open and short faults coverage. Following DFT guidelines during the board design process makes the board easier to test for defects and provides an opportunity to increase test coverage. As boards move through the manufacturing process, the goal is to reduce the number of defective boards produced. Defects need to be identified quickly so they can be repaired and processes can be adjusted. Boundary scan can also be used to test memory devices, configure programmable logic devices (PLD), and program flash memory devices. The boundary scan DFT guidelines in this eBook have been assembled over many years of experience by the technical staff of ASSET InterTech, Inc. The guidelines have been validated across a variety of simple and complex board designs.

Boundary scan DFT guideline highlights:

  • Proper buffering of Test Access Port (TAP) signals
  • Layout of TAP signals
  • Addressing different voltage levels on the scan chain
  • Using unused boundary scan cells
  • Testing memory, configuring programming configurable logic devices, and programming flash via boundary scan
  • Handling compliance enable pins
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