Testing DDR Memory with Boundary-Scan/JTAG | Third Edition

When failures related to memory devices occur, board test engineers often assume that the memory devices themselves are not causing the failure, since the memory chips are tested and qualified before they are assembled on a board. As a result, memory test failures frequently indicate a failure in the connectivity channel to/from the memory. Memory test methods such as Connectivity Test (CT) and/or Memory Access Verify (MAV) can perform thorough tests on the interconnects linking memory management units (MMU), field programmable gate arrays (FPGA), and processors to memory devices. Used together with JTAG-based methods, high test coverage of memory interconnects can be achieved.

The 1st edition of this eBook described DDR4 testing using CT and/or MAV actions in the production environment. For the 2nd edition, content was added providing an overview of DDR4 device structure, commands, and operation sequences. As this eBook enters its 3rd edition, content has been added describing some of the latest advancements in DDR memory, power, speed, and test technology. New memory devices such as DDR5 which utilize CT mode, and Graphics Double Data Rate 5 (GDDR5) SDRAM and GDDR6 Synchronous Graphics Random Access Memory (SGRAM) devices that implement forms of boundary-scan test technology, are described herein.


Madilyn Childress