Press Releases Archive | Page 4 of 12

New eBook shows how data mining shortens validation testing on serdes high-speed I/O buses

Tuesday, October 13, 2015

Statistical analytics goes beyond pass/fail testing to quantify the risks in a new design A new eBook published by ASSET® InterTech demonstrates how the data mining of validation test results can reduce the time an organization spends on validating serdes high-speed I/O (HSIO) buses and, at the same time,…

ASSET InterTech’s new data mining tool streamlines the validation of serdes high-speed I/O buses

Wednesday, October 7, 2015

Automatically analyzing margin data on high-speed buses reduces total test times and speeds systems to market faster The HSIO Validation Assistant (HVA), a new data mining tool for ASSET® InterTech’s ScanWorks® platform, automatically analyzes a database of signal integrity test data and quantifies the risk associated with potential design…

ASSET and Cadence IJTAG interoperability ensures IP re-use for advanced SoC and system diagnostics

Tuesday, October 6, 2015

Product demos at International Test Conference show growth of ecosystem for IJTAG embedded instrumentation standard At the International Test Conference (ITC) here this week, ASSET® InterTech (www.asset-intertech.com), a leading supplier of software and hardware debug, validation and test tools, and Cadence Design Systems Inc. (www.cadence.com) are demonstrating the interoperability…

New case study shows debugging multicore Linux software is accelerated when both trace and static tools can be used

Wednesday, September 16, 2015

Step-by-step approach reveals root causes in unexpected places Software engineers can spend days or weeks tracking down bugs in complex software for multicore systems-on-a-chip (SoC), often delaying new product introductions. A new eBook by ASSET® InterTech explains how developers can take advantage of both trace and static analysis tools…

At-speed in-system programming of flash memory enhanced with ScanWorks FPGA-Controlled Test and IJTAG

Tuesday, August 25, 2015

New capability takes advantage of an IJTAG network with programming engines embedded in an onboard FPGA Programming memory in-system, or after the devices have been soldered to a circuit board, is the most efficient method, but the challenge for design and manufacturing engineers has always been the slow speeds…

ASSET InterTech’s SourcePoint is first debugger to take full advantage of Intel Trace Hub

Thursday, August 13, 2015

Faster boot debug with insight into code execution and data from hardware and software sources SourcePoint® from ASSET® InterTech (www.asset-intertech.com), the leading supplier of software and hardware debug, trace, validation and test tools, is the first debug platform to provide real insight from Intel® Trace Hub to debug the Unified…

In-system flash programming 1,000x faster via IJTAG explained in new eBook

Tuesday, July 28, 2015

New faster methods for the in-system programming of onboard flash as well as I2C and SPI memory are explained in a new eBook published by ASSET InterTech. In-system programming has many advantages over standalone programming stations, but, until now, its programming speed has presented a challenge for design and…

Trace debug cuts through the complexity of SoC software, new eBook explains

Wednesday, May 27, 2015

Trace debugging takes advantage of intellectual property (IP) in processors to help software engineers track back to the root cause of a code bug and fix it. A new eBook by ASSET® InterTech, the leading supplier of software and hardware debug, validation and test tools, explains how valuable trace…

New eBook explains IEEE 1687 IJTAG standard IP re-use and portability, on-chip network and other innovations

Wednesday, May 6, 2015

The IEEE 1687 Internal JTAG (IJTAG) standard enhances the portability and re-use of embedded instrument intellectual property (IP) and defines a dynamically scalable on-chip network for instrumentation IP. A new eBook published by ASSET explains these innovations and others such as managing power domains with IJTAG, enabling instrument concurrence…

ASSET enhances software debug and hardware validation tools for Intel Broadwell-DE microarchitecture

Tuesday, April 21, 2015

Engineers designing microserver and other hyperscale workload systems based on the new Intel® microarchitecture codenamed Broadwell-DE will be able to quickly debug software and validate high-speed communications interconnects with ASSET® InterTech’s SourcePoint® and ScanWorks® platforms. The first generation of the Intel Xeon® Processor D family is based on the…

Press Releases