Press Releases Archive | Page 7 of 12

Testing DDR3 memory with boundary scan / JTAG explored in new eBook by ASSET InterTech

Tuesday, August 6, 2013

ASSET® InterTech (www.asset-intertech.com), the leading supplier of tools for embedded instrumentation, has issued a new eBook on how to test DDR memory with non-intrusive JTAG or boundary-scan (IEEE 1149.1) methods. A recent survey of engineers by the International Electronics Manufacturing Initiative (iNEMI) found that testing memory soldered to circuit…

ASSET InterTech and Arium join forces to increase visibility into complex system development

Tuesday, July 9, 2013

Arium’s Intel® and ARM® hardware-assisted debug tools will be integrated into ASSET’s ScanWorks® platform for debug, validation and test ASSET® InterTech (www.asset-intertech.com), the leading supplier of tools for embedded instrumentation, today acquired the business of Arium (www.arium.com), an Irvine, California provider of software debug tools for systems based on Intel®…

ASSET’s new eBook explains how to recover the costs sunk into circuit boards that will not boot

Thursday, June 6, 2013

A new eBook from ASSET® InterTech will help circuit board manufacturers who want to recover their investment in assembled boards that won’t boot – so called dead boards – and still maintain the tight production deadlines that constantly reduce the time they can spend on board debug. Even though “How…

ASSET ScanWorks is among the first tools to support the new on-chip Intel Silicon View Technology

Monday, June 3, 2013

With the introduction today of Intel® Silicon View Technology (Intel® SVT), ASSET® InterTech’s ScanWorks® platform for embedded instruments becomes the only platform in the industry that fully supports all three aspects of the new validation, debug and test capabilities which Intel is embedding into its processors and chipsets. Based…

How to do functional tests on I2C and SPI monitors with JTAG is explored in new eBook from ASSET InterTech

Wednesday, May 8, 2013

A new eBook from ASSET explains how the structural test methodology based on the IEEE 1149.1 boundary scan standard, known as JTAG, can apply functional tests to I2C and SPI system monitors during prototype board bring-up and later during circuit board production. Devices such as temperature sensors, electrical sensors and…

New PXI controller for ASSET’s ScanWorks platform supports four test technologies

Tuesday, April 23, 2013

With the new PXI-based controller for ASSET® InterTech’s ScanWorks® platform for debug, validation and test, engineers can test circuit boards with four different toolsets, each based on a different test technology. Operating from a personal computer and a PXI chassis, the new ScanWorks PXI-1000 controller can apply boundary-scan tests…

ASSET enhances IJTAG embedded instrumentation tool for debugging systems-on-a-chip (SoC) and testing circuit boards

Wednesday, March 27, 2013

Improvements to the graphical viewer and significantly faster performance are among the enhancements to ASSET® InterTech’s ScanWorks® IJTAG Test tool, with which engineers are able to access, control and automate the operations of test and measurement instruments embedded in chips. ScanWorks IJTAG Test was the first suite of tools…

New eBook explores CPU cache-as-RAM for board bring-up of non-booting prototype circuit boards

Tuesday, February 26, 2013

A new eBook from ASSET® InterTech, the leading supplier of tools for embedded instrumentation, takes a close look at how run-control tools can employ a processor’s on-chip cache memory instead of on-board RAM memory to boot non-booting prototype circuit boards. “Designers often face a catch-22. They have to diagnose a…

New eBook explores how manufacturing process variances affect throughput on high-speed serdes

Tuesday, February 12, 2013

Richardson, TX (February 12, 2013) – High-speed serdes (serializer/deserializer) links on printed circuit boards (PCB) sometimes don’t achieve their expected throughput rates because of process variances in manufacturing. A new e-book from ASSET® InterTech (www.asset-intertech.com), the leading supplier of tools for embedded instrumentation, explains the defects caused by process…

ASSET white paper explores solutions for diminishing test coverage from in-circuit test (ICT) systems

Wednesday, December 19, 2012

Non-intrusive software-based test methods deliver test coverage beyond the reach of legacy probes and bed-of-nails testers. A new white paper from ASSET® InterTech explains why test coverage from intrusive, probe-based in-circuit testers with their bed-of-nails fixtures is diminishing. The paper also describes software-based non-intrusive methodologies that test from the…

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