Press Releases Archive | Page 6 of 12

ASSET’s SourcePoint debug and trace tool now supports ThreadX operating system

Thursday, February 20, 2014

When software engineers have greater visibility into the context of operating system resources and the execution of multithreaded programs, they are able to accelerate code debug and deliver new products to market sooner. ASSET's SourcePoint® debugger now supports Express Logic’s ThreadX real-time operating system, giving development engineers multiple views…

Faster debug and trace using ARM System Trace Macrocell (STM) explained in new eBook

Tuesday, January 21, 2014

Accelerating software development by finding code bugs faster is quite challenging for systems-on-a-chip (SoCs) because of multithreaded software, multiple processing cores of different types and other factors. A new eBook published by ASSET® InterTech explains System Trace Macrocell (STM), a relatively new code tracing capability that gives much more…

ASSET's Arium software debugger turbo charges ARM’s System Trace Macrocell

Tuesday, October 29, 2013

Accelerating the tracking of software bugs through mountains of trace data back to their root causes shortens the development of multicore, multithreaded systems-on-a-chip (SoC) by months and delivers new products to market sooner. Enhancements to ASSET InterTech’s Arium hardware-assisted SourcePoint® debugger optimize the processing of ARM’s System Trace Macrocell…

ASSET's Arium tools will debug ARM code in TI's multicore OMAP architecture

Tuesday, October 22, 2013

Designers of systems based on one or more Texas Instruments (TI) OMAP application processors with ARM cores can now debug software and firmware code faster with ASSET® InterTech’s Arium SourcePoint® debugger for ARM. The Arium SourcePoint debugger has a number of advanced capabilities, including address translation, dynamic page translation,…

ASSET's Arium software debugger supports Intel's new Silvermont microarchitecture with Real-Time Instruction Trace (RTIT)

Tuesday, October 15, 2013

Software engineers debugging code for multicore systems-on-a-chip (SoC) based on Intel®’s new Silvermont microarchitecture will be able to take advantage of Silvermont’s Real-Time Instruction Trace (RTIT) capability with ASSET® InterTech’s Arium SourcePoint® debugger. SourcePoint is able to extend its debug and trace capabilities over the entire Silvermont SoC. The instruction…

ASSET's Arium tools support Intel C2000 Atom, accelerating software debug for new class of microservers

Tuesday, October 8, 2013

Designers of microservers based on the new Intel® C2000 Atom™ system-on-a-chip (SoC) will be able to debug software and firmware faster because of the powerful tools in ASSET® InterTech’s Arium SourcePoint® debugger. “The increased complexity of the C2000 Atom architecture can be challenging to software engineers who are trying…

ASSET's Arium tools will debug ARM code in TI's multicore KeyStone architecture

Tuesday, October 1, 2013

Designers of applications like networking systems, imaging, high-performance computing, gaming, media processing and others that are based on processors with the multicore Texas Instruments (TI) KeyStone II architecture now have a powerful set of software and firmware debugging tools in ASSET® InterTech’s Arium SourcePoint debugger for ARM. “Software bugs…

ScanWorks demonstrates compatibility with new IJTAG standard for embedded instruments

Tuesday, September 10, 2013

Full compatibility with the soon-to-be-ratified IEEE P1687 Internal JTAG (IJTAG) standard for ASSET® InterTech’s ScanWorks® platform for embedded instruments will mean that developers and test engineers will have a powerful suite of IJTAG tools to ensure the standard’s rapid adoption in the industry. At the International Test Conference (ITC)…

ASSET announces new bundle of validation and test tools for Intel Xeon, Core and Atom designs

Tuesday, September 10, 2013

ASSET, the leading supplier of tools for embedded instrumentation, announced at the Intel Developers Forum a new bundle of ScanWorks HSIO tools for the Intel Architecture (IA). Previously licensed separately, ScanWorks HSIO for IA now delivers greater value to developers by bundling tools for all three Intel silicon brands,…

Programming on-board flash and EEPROM memory at SPI bus speeds from an FPGA is explained in new eBook

Wednesday, September 4, 2013

Designers and manufacturing engineers face challenges when it comes to programming flash and EEPROM memories that are already soldered to a circuit board. Often, the software or firmware content of these memories has not yet been completed when hardware prototypes are being validated and tested prior to volume manufacturing.…

Press Releases