Hardware Validation

Statistical analytics goes beyond pass/fail testing to quantify the risks in a new design A new eBook published by ASSET® InterTech demonstrates how the data mining of validation test results can reduce the time an organization spends on validating serdes high-speed I/O (HSIO) buses and, at the same time,…

Automatically analyzing margin data on high-speed buses reduces total test times and speeds systems to market faster The HSIO Validation Assistant (HVA), a new data mining tool for ASSET® InterTech’s ScanWorks® platform, automatically analyzes a database of signal integrity test data and quantifies the risk associated with potential design…

ASSET, the leading supplier of tools for embedded instrumentation, announced at the Intel Developers Forum a new bundle of ScanWorks HSIO tools for the Intel Architecture (IA). Previously licensed separately, ScanWorks HSIO for IA now delivers greater value to developers by bundling tools for all three Intel silicon brands,…

Richardson, TX (February 12, 2013) – High-speed serdes (serializer/deserializer) links on printed circuit boards (PCB) sometimes don’t achieve their expected throughput rates because of process variances in manufacturing. A new e-book from ASSET® InterTech (www.asset-intertech.com), the leading supplier of tools for embedded instrumentation, explains the defects caused by process…

Bandwidth tests often detect degraded performance on DDR, PCI Express, Intel QPI, USB and others high-speed buses Richardson, TX – A new white paper from ASSET® InterTech (www.asset-intertech.com), the leading supplier of tools for embedded instrumentation, points out how increasing bus speeds on circuit boards could create havoc for…