Chiplet-based multi-die devices, as products of a heterogenous integration design methodology, play an important role in today’s chip design and implementation strategies. The drive to implement multi-die devices began in the 1970’s with a packaging innovation approach consisting of placing multiple interconnected chips on a package-scale substrate. These devices became known as multi-chip modules (MCMs). Over time, additional packaging innovations emerged such as System in a Package (SiP), System on Integrated Chip (SoIC)™, 2.5D-Integrated Circuits (ICs) and 3D-IC packages. Multi-die packaging innovations has allowed the semiconductor industry to create smaller, faster, configurable, and lower power ICs.

Accessing and operating embedded instrument IP has not been easy. In fact, it’s been a challenge. But the recently ratified IEEE 1687 Internal JTAG (IJTAG) standard for embedded instruments is changing the way the industry thinks about chip characterization and debug, portable IP, re-targeting test vectors, embedded TAPs, on-chip instrument networks, and how to re-use all that instrumentation embedded in chips to validate, test and debug not only chips, but circuit boards as well.

What happens when you’re mixing multiple embedded TAPs – eTAPs? Like when TAPs for IEEE 1149.1 boundary scan, JTAG software debug ports (ARM DAP, Intel ITP) and IJTAG instruments are all in the same SoC design? You might be in for an ugly surprise. The eTAPs accessed through the chip-level TAP might not do what you had in mind.

This eBook provides a tutorial on the approved IEEE 1687 Standard for Access and Control of Instrumentation Embedded within a Semiconductor Device, which is commonly referred to as the Internal JTAG or IJTAG standard.

Without security, what do we expect the hackers to do? Face the facts: There are no industry standards for semiconductor and board test security. None in the JTAG and IJTAG standards. So all the board/system developers can do is integrate a variety of different semiconductor security protocols. But some chips have no test security at all!

Learn what IEEE 1149.7 is all about, what its objectives are, how it works, its implications for debugging SoCs and 3D chips, and for testing circuit boards. Several illustrations show IEEE 1149.7 topologies. Scan-state sequences and flow charts clarify IEEE 1149.7’s terminology.

For years chip vendors have embedded test and measurement instruments into their chips so that the chips themselves could be tested. Now, the industry has realized that this wealth of validation, test and debug instrumentation can be put to wider use on circuit boards and in systems. The new IEEE P1687 IJTAG standard is a step in this direction. This e-book describes the objectives of the IJTAG working group and the resulting IJTAG on-chip embedded instrumentation architecture.