Chiplet Interconnect Testing Using JTAG/Boundary Scan
Chiplet-based multi-die devices, as products of a heterogenous integration design methodology, play an important role in today’s chip design and implementation strategies. The drive to implement multi-die devices began in the 1970’s with a packaging innovation approach consisting of placing multiple interconnected chips on a package-scale substrate. These devices became known as multi-chip modules (MCMs). Over time, additional packaging innovations emerged such as System in a Package (SiP), System on Integrated Chip (SoIC)™, 2.5D-Integrated Circuits (ICs) and 3D-IC packages. Multi-die packaging innovations has allowed the semiconductor industry to create smaller, faster, configurable, and lower power ICs.
With this as a background, this eBook discusses how advanced packaging methods used in the semiconductor industry today have extended Moore’s Law through the implementation of chiplet-based multi-die device designs. Similar to packaged chips placed on a printed circuit board, interconnects between chiplets within multi-die packages must undergo testing for structural integrity. Structural testing involves the application of digital test vectors that are formatted for use on chip-level ATE.
- Use of JTAG IEEE 1149.1/1149.6 for testing of single-ended and differential chiplet-based die-to-die interconnects
- Technology options and signaling schemes for chiplet-based die-to-die interconnects
- IEEE 1450 – Standard Test Interface Language (STIL) for chiplet-based multi-die device testing on Automated Test Equipment (ATE)
- Wagner patterns versus alternatives for optimizing test coverage and diagnostics
- Benefits of improved device performance through the identification of structural defects using STIL produced by ScanWorks