One-shot pass/fail validation testing won’t quantify the risk of faults on serdes and high-speed I/O (HSIO) buses, but data mining with statistical analytic tools will. In fact, you’ll see how close the bus is relative to its eye mask and where those failures are just waiting to happen. Why risk the crashes, poor performance and dissatisfied users?
Following a defined methodology is an essential step in ensuring signal integrity on Intel® Core™ designs. An approved three-phase process is as follows:
This document provides a detailed look at the use of boundary-scan test, processor-controlled test and high-speed I/O validation when applied to the Intel® microarchitecture code name Haswell design. In particular you will learn:
Following a defined methodology is an essential step in ensuring signal integrity on Intel® Xeon® designs. An approved three-phase process is as follows:
Designing sufficient operating margins into today’s high-speed printed circuit boards has become a very tough job. Especially challenging are those high-speed serial I/O and DDR3|DDR4 memory buses. Measuring signal integrity on a lane or two here and there won’t cut it anymore.
Boards and chips keep getting denser, faster. And the speed is higher so they’re a whole lot more sensitive. Slight variances or defects cause intermittent crashes and performance degradation. And the negative effects interact. Welcome to living “on the edge.”
Remember test pads? Small contact points on a board’s interconnect buses with physical access for test purposes? No more. Or at least not for high-speed serial interconnects like PCI Express, Fibre Channel,10-Gbps Ethernet, InfiniBand®, Intel® QuickPath Interconnect (QPI) and the like.
Ever wonder why your notebook is running slower than ever, or keeps hanging and crashing? It could be signal integrity.
Copyright ©2024 ASSET InterTech, Inc. All rights reserved.
