Embedded software tuning on an SoC for DDR memories is the next evolution in technology and it is available today. The technology should not only provide the ability for automatic DDR calibration optimization but allow interactive tuning adjustments. The interactive adjustments are necessary to handle component changes, environmental impacts, and engineering experiments in support of the designer as they ensure optimum settings for the DDR memory controller and PHY in their designs.
The technology must be backed up with strong memory test infrastructure from structural-to-functional. The functional test must include memory traffic generation which includes noise injection. Without a strong memory test suite, it is not possible to verify the performance that results from the register value changes that control the memory transactions from SoC-to memory components.
This eBook will cover DDR calibration backgrounder, theory of operation and finally a practical application on the SABRE Lite with a NXP i.MX 6Quad SoC with 1Gib of DDR3 memory installed.
With ASSET’s 20-year history in test, the addition of Processor-based Functional Test for DDR to the ScanWorks platform is a natural engineering progression of the technology.