Case Study: How ASSET InterTech Transformed a Defense Contractor's Programming Process, Saving Over 11 Hours and Thousands of Dollars
Background
A leading defense contractor, referred to as “the client” due to a non-disclosure agreement, faced significant challenges with their FPGA programming process. The client was using a Xilinx XQ7A200T FPGA and encountered issues with their flash programming process. The standard SPI action took an excessive 11 hours to program the flash memory, which was not sustainable for their operations.
The Challenge
The client needed a reliable and efficient solution to reduce the programming time and ensure the reliability of the FPGA programming process. The existing process was not only time-consuming but also prone to errors, causing significant delays and potential redesigns of test platforms. The client was under pressure to resolve these issues within a week to avoid switching to an alternative plan that involved redesigning the test platforms and adding vendor programming pods to all stands.
The Solution
ASSET InterTech, a leader in boundary-scan (JTAG) and embedded instrumentation, was approached to address this critical issue. The collaboration involved key personnel from both organizations, including the Program Director from the client side and the team at Asset InterTech.
1. Initial Diagnosis and Communication:
The Program Director reported the issue of the flash programming process hanging and the excessive time required for programming the flash memory.
The team at ASSET InterTech began by diagnosing the problem, asking detailed questions about the setup, including the controller used and the specific actions that were hanging.
2. Technical Adjustments:
The Program Director made several adjustments, such as changing the action to check only the device ID.
The team at Asset InterTech suggested removing the image file from the action to separate the parsing of the Intel Hex file and communications with the SPI IP instrument.
3. Development and Testing:
The development team at Asset InterTech was involved to provide a deeper technical analysis and potential fixes.
After several iterations and adjustments, including modifying file and register locations, the team was able to find a reliable solution.
The Results
The collaborative efforts between the client and ASSET InterTech led to a significant breakthrough. The programming time was reduced from 11 hours to just 3.3 minutes, a remarkable improvement that saved the client substantial time and resources. The Program Director expressed their satisfaction, stating, “I wanted to let you guys know, you fixed it! I just finished a dozen iterations loading, erasing and programming/verifying it seems to be reliable. The program managers are happy, the programming time dropped from 11 hours (standard SPI action) to 3.3 minutes. Thank you for your support”.
Cost Savings
By reducing the programming time from 11 hours to 3.3 minutes, the client saved approximately 10.95 hours per programming cycle. Assuming an average labor cost of \$175 per hour, this translates to a cost saving of \$1,916 per cycle. Given that the client performs this programming process 50 times a year, the annual savings amount to \$95,800. Additionally, the reduction in programming time allowed the client to reallocate resources to other critical tasks, further enhancing operational efficiency and cost-effectiveness.
Conclusion
This case study highlights the importance of collaboration and technical expertise in solving complex engineering challenges. ASSET InterTech’s proactive approach, technical adjustments, and dedicated support played a crucial role in resolving the client’s FPGA programming issues. The successful reduction in programming time not only saved the client time and money but also ensured the reliability and efficiency of their operations.
