High-Speed I/O Design Guidelines

I was reading a Design Guidelines document recently that nicely summarized what to watch out for when designing circuits with high-speed I/O. There are so many things that can go wrong, so careful design and accurate measurements are essential.

High-speed I/O design is a complex topic, and there are many references available on the subject. Examples include Advanced Signal Integrity for High-Speed Digital Designs by Stephen H. Hall and Howard L. Heck, and High Speed Digital Design: A Handbook of Black Magic by Howard Johnson and Martin Graham. As high-speed buses such as PCIe, HDMI, and XLAUI exceeding 5 GT/s are now becoming commonplace on everything from smartphones to notebooks to routers, a designer’s job is becoming more and more complicated. Even assuming all the right practices are followed, and exhaustive simulations performed, accurate measurements of what is happening at the silicon receivers are necessary to warrant a system’s performance.

Here’s a partial list of what designers need to worry about when designing PCBs with higher speed buses:

  1. Intra-pair total length matching should be <= 5mils.
  2. For length running skews > 25 mils, compensation should be made within 600 mils.
  3. Serpentine “bumps” can be added to the shorter member of a pair to reduce skew.
  4. Where bumps are needed, the original inter-pair spacing should be preserved.
  5. Avoid routing nets near Voltage Regulator induced noise, or limit the noise induced by fast switching VR nodes.
  6. Avoid routing over a split power plane.
  7. Avoid 90-degree routing which can result in accumulated common mode noise effects.
  8. Fan out narrow traces (which may be necessary to escape a tight pin field area) within 100 mils to reduce impedance discontinuity and trace loss.
  9. The “dog bone” (segment between the component pad and an inner layer transition) should be less than 30 mils height and 5 mils width.
  10. The maximum routed length under a pin field is 1.5”.
  11. Don’t route over pin fields that have a high magnitude of transient currents, like power delivery pin fields.
  12. If you have to length-match within a pin field, place the serpentine bumps near ground vias, or similar via types (i.e. TX via over TX trace, RX via over RX trace).
  13. Avoid layer transitions wherever possible.
  14. If you have to do a layer transition, reduce solution space by 5”.
  15. Reduce discontinuities caused by layer transitions and via stubs along the signal path.
  16. Place vias symmetrically to avoid differential to common mode conversion.
  17. Between a via pair, the pitch must be between 25 and 50 mils. The gap between any two different via pairs must be greater than 50 mils.
  18. Each high-speed signal via should have a Vss via within a 50 mils gap.
  19. Be sure to strip via pads on un-routed layers.
  20. Backdrill to remove the via stub of pressfit connectors for boards thicker than 73 mil.
  21. Minimize capacitance due to lead length protrusions from THMT components.
  22. The same package size of capacitor should be used for each signal in a differential pair.
  23. Pad sizes for capacitors are to be the minimum allowed per DFM to minimize parasitic effects.
  24. Avoid placing capacitors next to devices that generate heat, such as power FETs (some capacitors perform at less than 50% of their nominal value when exposed to heat).
  25. Use of through-hole connectors is preferred (press fit connectors induce vertical coupling cross-talk effects).
  26. Some critical pins should never have any trace routing connected whatsoever, lest they act as antennae, transmitting induced crosstalk into adjacent traces.

The list goes on and on, and indeed as Dr. Johnson has said, some of this is “Black Magic”. An error on any of the above can induce increased crosstalk, inter-symbol interference, jitter, bit errors, and other irregularities as well as reducing or closing the margin on any given bus.

One obvious consideration is NEVER to put a test pad down on a high-speed bus; almost all PCB Design Guidelines documents emphasize that fact. For more information on this subject, see my previous blog on Test Pads on High-Speed Nets. This is driving more and more companies away from legacy products such as In-Circuit Test (ICT) and oscilloscopes, and towards non-intrusive validation and test technologies based upon embedded instrumentation.


Alan Sguigna

4 Responses

  1. Thank you Girish.
    Could you elaborate on the context of your question: are you really asking if there is a difference in the PHY margin (eye diagram) if the die is wire-bonded versus placed in a flip-chip carrier? Or are you addressing the physical differences in the connection between the two?

  2. Alan,
    My question about the IO design itself. I mean, can we use one IO for both flip-chip and wire-bond? or the IOs are separately/specially designed for flip-chip & wire-bond.

  3. Girish,
    In general, chip designers strive to make “one die” with “one PHY” during logical design and to submit that one logical design for packaging. There is a fundamental difference in making a die for a wire-bond (bond pads around the periphery) and making a die for a flip-chip (bumps distributed across the die) — the change happens during the last phase of design, physical layout. There aren’t too many companies that make die for both – they usually make die for one or the other (only go through physical layout once).
    The worst case design is the wire-bond — largest pads, most environmental issues (capacitance, resistance, etc.), and most uncertainty since the bond wires can touch or bend or be non-uniform in shape, etc. If the chip is logically designed for the wire-bond and includes enough tuning space to accommodate the possible changes and challenges of the wire-bond package, then it has more than enough adjustment and margin for a flip-chip design. So, if a company actually designs a chip for both, then they will most likely design it to the drive-specification and give it the tuning margin to handle the wire-bond — and will then submit it to different physical layout processes to end up with two different die masks that result in two different die types coming out of the fab. The different die then go to different packaging processes.
    In summary, if a die is designed for wire-bond, it can be reused for flip-chip. However, if a design is made specifically for the higher-performance flip-chip (optimized to have smaller PHY drive, smaller bumps, shorter connections, etc.), then it most likely cannot be reused for wire-bond, without going through logic re-design and different physical layout.
    Hope that helps.