Block diagram of ScanWorks Processor-based Functional Test for DDR for NXP i.MX 6Quad
Block diagram of ScanWorks Processor-based Functional Test for DDR for Zynq-7000
SourcePoint by ASSET InterTech logo for Partners.
ASSET’s SourcePoint debugger examining ThreadX resources for the active software thread.
ASSET HSIO Eye Diagram with Mask
Teradyne’s PXI Express-based High Speed Subsystem (HSSub)
Intel® Atom™ processor
Block diagram of a memory test instrument, extracted from our Memory Test eBook.
ScanWorks high-speed PCI Express (PCIe) bus controllers
ScanWorks® eye diagram from Intel® IBIST
Four Port Remote Instrumentation Controller.
ScanWorks® FPGA-Controlled Test (FCT) coverage diagram.
ScanWorks® Component action user interface.
ScanWorks® HSIO for Intel® µ-architecture codenamed Haswell
Capable of running ScanWorks® boundary-scan tests
ScanWorks® Component Action graphic
Single-Port Remote Instrumentation Controller
Worldwide Test via the Internet
LGA1366 Interposer for Intel® Xeon® Processor 5500 Series and Intel® Core™ i7 processors. Used to access the CPU's... more
ScanWorks® for Intel® Xeon® Processors 5500 Series – Block Diagram
ScanWorks® for Intel® Xeon® Processors 5500 Series on Laptop
ScanWorks® IJTAG Screen – Define an IJTAG Instrument Action
Glenn Woppman, President & CEO, ASSET InterTech
Tim Dehne, member of the ASSET board of directors.
FPGA-Controlled Test (FCT) Backgrounder
Embedded Instrumentation Ushers in a New Era for the Test and Measurement Industry
Driving embedded instrumentation for chip, board and system validation, debug and test