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New eBook explores how manufacturing process variances affect throughput on high-speed serdes

Tue, February 12, 2013
How to Avoid Poor Serdes Performance Caused By Circuit Board Manufacturing Variances

Richardson, TX (February 12, 2013) – High-speed serdes (serializer/deserializer) links on printed circuit boards (PCB) sometimes don’t achieve their expected throughput rates because of process variances in manufacturing. A new e-book from ASSET® InterTech (www.asset-intertech.com), the leading supplier of tools for embedded instrumentation, explains the defects caused by process variances and how they can be detected with minimum effects on the manufacturing line. 

Entitled “How to avoid poor serdes performance caused by circuit board manufacturing variances”, the new e-book includes a case study which analyzes the effects of manufacturing variances on a typical serdes trace on a PCB. A tool also included in the e-book can be used by engineers to calculate resistance and impedance on transmission lines. 

“Validating the design of high-speed serdes interconnects on prototype PCBs does not assure that the serdes will maintain the validated level of performance once high-volume production begins,” said Arden Bjerkeli, director of customer experience for ASSET and one of the authors of the e-book. “Manufacturing variances can degrade serdes performance and are all too common. Now embedded instrumentation offers a number of solutions for detecting process variances with minimal impact on product throughput.”

The e-book "How to avoid poor serdes performance caused by circuit board manufactuirng variances" is available now.