Testing DDR4 Memory with Boundary Scan/JTAG

Double Data Rate 4 (DDR4) memory devices are becoming more prevalent on today’s digital high speed designs. DDR4 memory devices have more bandwidth, higher DIMM capacities, and lower power consumption than their predecessors. Despite this advancement in on-board memory technology, test engineers tasked with verifying the structural integrity of interconnects around DDR4 memory devices on a printed circuit board (PCB) face the same test challenges as in the past. Once the DDR4 memory is placed on a PCB, structural testing by intrusive test technologies is challenged; being based on mechanical probes or bed-of-nails fixtures, these require physical access points that are problematic because of board density and because such test points introduce signaling anomalies that compromise integrity or reliability of memory function. The non-intrusive nature of boundary scan/JTAG overcomes these challenges.

Testing-ddr4-memory-with-boundary-scan-jtag-4webASSET InterTech’s ScanWorks® Boundary-Scan Test (BST) can facilitate structural (shorts and opens) testing on control, address, and data lines of on-board DDR4 memory devices. Whether through the built-in test capability of DDR4 memory devices known as the Connectivity Test (CT) mode or by using a Memory Access Verify (MAV) action, testing DDR4 devices with ScanWorks is fast and easy. CT mode test scripts or MAV models for DDR4 can be downloaded from ASSET’s Model Library and rapidly integrated into ScanWorks. Test actions can then be created and applied to on-board DDR4 memory devices. With ScanWorks, DDR4 test actions for shorts and opens testing can begin with board prototypes in development and continue on to production units in manufacturing.

We recently published a new eBook that describes the various methods that you can use with ScanWorks Boundary-Scan Test to accomplish your DDR4 testing.

Check out this eBook, “Testing DDR4 Memory with Boundary Scan/JTAG”.

Michael Johnson