Is that old bed-of-nails rather prickly these days?
Legacy In-Circuit Test (ICT) has been diminishing in value for a long time. Let’s explore some of the current technical issues with ICT as test access on new circuit board designs continues to disappear.
The test access issue continues to plague the printed circuit board manufacturing industry. The International Electronics Manufacturing Initiative (iNEMI) considers declining test access to be one of the critical issues of our decade (http://www.inemi.org/cms/projects/test/index.html). How do OEM and EMS firms keep their production yields up and quality high in the face of diminishing test access? Globally, there is a fever pitch of discussion within the hardware design and test engineering disciplines as to how to address this.
But even though test access by itself is accelerating the replacement of ICT and adoption of new test strategies, the ICT issue actually has numerous other technical dimensions. What follows is a fresh catalog of the issues.
High-Speed Buses – Test Pads Part 1
Putting test pads down on high-speed I/O is of course problematic. Beyond 4.6GHz, signal attenuation from the extra metal on a via stub causes major signal integrity issues.
There have been several attempts to address this issue on ICT. One is with bead probes, whereby tiny beads of solder are placed directly on a high-speed interconnect as landing pads for flat fixture probes.
Its unique licensing terms, need for special CAD support, and custom ICT requirements have greatly restricted its adoption.
Another solution is powered opens (PO). This is a mechanism whereby boundary scan is used as the stimulus (instead of nails) required for a capacitive sensing plate to detect opens. This solution is limited by the following issues:
- Source devices must be populated on the board, presenting fixture mechanical and logistical problems.
- PO is an opens testing methodology; does not detect most shorts.
- Does not work on input-only cells.
- Two opens on a differential pair will escape detection.
- On AC-coupled differential pairs, shorts on the connector side can escape detection.
It is worthy to note that powered opens (and unpowered opens for that matter) was originally meant to couple a signal from a QFP device lead frame. Lead frames have mostly gone away. Also, connectors with recessed pins or lots of ground shielding get no coupling.
Boundary Scan on ICT
Boundary scan can of course be run natively on ICT as well as downstream in production testing. However, native boundary scan on ICT is typically subject to the following limitations:
- Is subject to much slower TCK rates.
- Typically doesn’t have scan path verification as a separate, fully-featured action.
- Tests between boundary scan nets and nails need to be created manually (i.e. no automation), do not test to non-adjacent nets, are subject to ground bounce for large-pin-count tests, and are extremely difficult to debug.
- Lacks the power and usability of dedicated boundary scan testers, particularly in the areas of features such as IEEE 1149.6, SPI/I2C testing, memory access verification, flash programming, and so on.
Moreover, you might think you are getting shorts coverage on ICT from boundary scan, but in many cases you’re not. Especially as applies to DDR memory nets, the boundary scan cells are typically output-only and not self-monitoring, so there may be no shorts coverage.
So given the limitations of powered opens for opens coverage and boundary scan for shorts coverage, these two technologies provide only a subset of test coverage that is needed.
High-Speed Buses – Test Pads Part 2
Ever been in one of those meetings where Design Engineering and Test Engineering try to define where to put via stubs and test pads and whether those create layout problems and signal integrity issues? These meetings are often quite contentious because of the trade-offs introduced. Test Engineering needs as much test access as possible. Design Engineering is trying to get a product to market and looking for ways to fast-track the schedule.
Life can be a whole lot less stressful when, during the new product introduction phase, the engineering groups can agree on a test strategy that doesn’t compromise time-to-market and product quality.
It is well-known that ICT probes on a board create significant strain. This effect is exacerbated by lead-free solder. Frequently, solder problems and component damage is introduced due to this flexing. This harm may not be detected on ICT as it manifests itself after the strain is removed and in fact may not even be detectable in production functional testing at all because the defect is latent – to be discovered later by the customer.
Many ICT engineers will testify that sometimes it takes two or even more insertions to make physical contact with ICT probes. This is worsened by higher-density designs and finer-pitch plated through-hole. False failures and multiple insertions extend test time and reduce the desired deterministic nature of testing.
Heat sinks pose a particularly difficult problem for ICT. Due to fixture access issues, most PCBs are tested at ICT without the heat sinks in place. Downstream, on the finished assembly, new structural defects may be introduced after the heat sinks are bolted on. And when a reworked board needs to go back to ICT for testing, the heat sinks don’t come off easily.
Keeping the Board “Safe and Cool”
This is where things get nasty for ICT. It requires that a board be in a quiescent state. Running clocks on the PCB or the fixture is no-no: signal integrity and noise issues make the nails act like hundreds of little antennae.
Bed-of-nails fixturing was a good idea when things were at DC frequencies, but nowadays many test technologies require the devices to be populated and cores running. This clearly presents issues with power and cooling. Many older-model ICT testers cannot supply the power needed anyway.
Post-Assembly Defect Introduction, and the Limitations of Functional Test
There are ways around some of these limitations of course. Only stuff the board with the minimal number of components. Put nails everywhere it’s humanly possible. Use plated through-hole testpoint access to BGA sockets and connectors where applicable. Then test the board with ICT, and pass it down the line for final assembly and functional test. You can rest easy that ICT will have caught at least some of the structural defects.
But it’s not that easy. More structural defects, particularly opens and component damage, can be an outcome of the final assembly process. And just running functional test will not catch the full spectrum of structural defects that may have been introduced. Differential high-speed nets in particular, since they run in common-mode, can be immune to some shorts and opens and continue to run. And defects on some clock and control signals will also allow the bus to continue to run, albeit at a degraded performance. Regular OS-based functional test will probably not catch these and will result in test escapes.
Now, don’t get me wrong. Bed-of-nails still has its place. In fact it remains the best way to do things like unpowered testing, measuring component values, testing voltage regulators, etc. It’s simply that there are more and more issues emerging with ICT-based test strategies, opening the door for a migration to higher test coverage, less intrusive, less expensive software-based solutions.
Learn more about what ASSET’s ScanWorks Platform for Embedded Instruments has to offer when faced with limited access.