More Problems with In-Circuit Test

I found an interesting article on the pros and cons of ICT recently at The document is a little dated (it looks like it was written in 2007), so I thought I would capture the essence of what was listed in this paper and add in some comments as well:

Advantages of ICT

  1. Relatively easy to program
  2. High fault coverage for manufacturing defects
  3. Test results relatively easy to interpret
  4. Not limited to use by test technicians, can easily be used by production operators
  5. Short test time (Usually 1-2 minutes per assembly)
  6. Very efficient for medium to high volume through-hole conventional assemblies
  7. Relatively low maintenance costs
  8. Wide choice of ICT platforms and manufacturers
  9. ICT can be configured in terms of node count to your exact requirements i.e. no need to pay for redundant features

Disadvantages of ICT

  1. High capital outlay
  2. Each product needs its own test fixture
  3. Not suitable for small batch products where test fixture/programming cost may prove prohibitive
  4. PCB densities sometime make probing difficult if not impossible
  5. Test contact failures can arise when test pins do not make proper contact with the appropriate test pads
  6. Test pins need to be regularly cleaned and replaced
  7. Some components may be shielded by other components so no test access can be achieved
  8. This is not a functional test although some of the larger machines can power the assembly up and simulate functional conditions
  9. Struggles with high density, small package size SMT components
  10. Large node count assemblies may need you to purchase additional driver/receiver cards – which are not cheap
  11. Equipment manufacturers offer relatively expensive support contracts

Since 2007, there have been even more changes in printed circuit board characteristics that challenge the continued use of ICT. Some of these were elaborated on in my previous Blog: I thought that in particular Item #7 under Disadvantages listed above needed some elaboration. Supply voltages have been steadily decreasing to address power dissipation on today’s dense circuit boards. Nowadays, some devices have less than a 250mV difference between logic high and logic low, and have become more sensitive to overvoltage conditions. So two new trends have emerged:

  • It is more difficult for ICT to accurately sense low-voltage digital logic levels
  • Electrical overstress (EOS) from backdriving can damage components.

The latter is becoming extremely critical for ICT. When a probe applies digital logic vectors to an IC, it may briefly force an above-normal current in or out of the device. Called “backdriving”, this can cause device damage.

There are several ways to address the EOS backdriving issue. One way is to use new ICT technology which includes ICT pin drivers with dedicated circuitry to monitor the output current delivered to each node on the board in real time. Another way is to use embedded instrumentation-based technologies whose mission-mode logic levels are consistent with devices’ voltage-swing standards, such as boundary scan (IEEE 1149.1 and 1149.6), processor-controlled test, and I/O BIST.


Alan Sguigna