Intel x86 Design for Debug Guidelines

The ScanWorks Embedded Diagnostics solution for Intelâ x86 provides local and remote debugging capability via the CPU debug port instrument. Such capabilities include dumping of forensic data during a system crash or hang (i.e. register, memory and I/O), setting of breakpoints, and single-stepping through code.  ScanWorks Embedded Diagnostics thus acts as an embedded JTAG debugger, in-situ within an on-board service processor. It is thus hardware- and distance-independent and can be used anytime, anywhere in the world on numerous systems in parallel. This provides an extremely effective means of debugging BIOS, device driver, OS kernel, and intermittent or catastrophic hardware and software failures in the lab and in the field.

ScanWorks Embedded Diagnostics for x86 systems requires a connection between the embedded service processor (BMC, FPGA or other) supporting run control and the target Intel CPU(s). The nature of these connections is described herein.

The following table describes the ten signals that ASSET recommends:

 

Platform Signal

XDP signal

Direction (wrt XDP)

TRST_N

TRST_N

OUT

TCK (CPU0)

TCK0

OUT

TMS

TMS

OUT

TDI

TDI

OUT

TDO

TDO

IN

PREQ_N (CPU0)

OBSFN_A0

OUT

PRDY_N (CPU0)

OBSFN_A1

IN

DBR_N

HOOK7

OUT

RESET_N

HOOK6

IN

PWRGOOD

HOOK0

IN

 

With respect to signal direction, that for the service processor would be the same as that for the XDP.

Some level translation to/from the service processor may be required.

As well, some switching/multiplexing between the XDP connector and the service processor (BMC or FPGA) source may be required. The XDP_PRESENT_N signal can be used as a means of controlling these switches.

Should there be any constraints in terms of XDP GPIO access, it is possible to work with smaller access signal configurations. The pin access configurations and the levels of debug which they support are described below. PWRGOOD can be equipped optionally for all configurations/levels and can be invoked optionally based upon real-time requirements; a reliable means of knowing that power to the CPU is live is recommended.

Level 0: TAP (TRST_N, TCK, TMS, TDI, TDO) signals only.

Supports debug mode entry/exit, all register/memory/IO read/write, setting breakpoints, and single-stepping of code.

Breakpoint-getting can only be executed via JTAG polling from BMC/FPGA (inefficient).

Level 1: TAP, PREQ_N, PRDY_N.

Supports all of Level 0 functionality.

Allows for more efficient debug mode entry and sensing. This level thus eliminates the need for breakpoint hit detection.

Level 2: TAP, PREQ_N, PRDY_N, DBR_N, RESET_N

Supports all of Level 1 functionality.

Initiate and sense reset.

Enter debug mode at reset capability.

 

Alan Sguigna