What happens when you’re mixing multiple embedded TAPs – eTAPs? Like when TAPs for IEEE 1149.1 boundary scan, JTAG software debug ports (ARM DAP, Intel ITP) and IJTAG instruments are all in the same SoC design? You might be in for an ugly surprise. The eTAPs accessed through the chip-level TAP might not do what you had in mind.
Not long ago, the embedded instruments for each application domain probably had their own access mechanism. But now, practically all on-chip instruments are accessed through the chip’s primary JTAG TAP. Subordinated below this TAP will be IJTAG networks and/or eTAPs that serve individual instruments. All these eTAPs behind the one chip-level TAP can cause access conflicts among the instruments and the application tool chains.
This eBook specifies a best-practices proposal that avoids the problems. And those nasty surprises.