Google search

Testing DDR3 memory with boundary scan / JTAG explored in new eBook by ASSET InterTech

Tue, August 6, 2013
Testing DDR3 Memory with Boundary Scan / JTAG

ASSET® InterTech (, the leading supplier of tools for embedded instrumentation, has issued a new eBook on how to test DDR memory with non-intrusive JTAG or boundary-scan (IEEE 1149.1) methods. A recent survey of engineers by the International Electronics Manufacturing Initiative (iNEMI) found that testing memory soldered to circuit boards is a major problem for system manufacturers.

“The ability to thoroughly test, characterize and diagnose problems with soldered-down memory is one of the most pressing problems in the industry,” said the author of the new eBook, Kent Zetterberg, product manager, ASSET InterTech. “Because DDR3 memory chips have become so prevalent in high-speed systems, I used this technology as the basis for explaining how JTAG or boundary-scan methods can be integrated into every step of a system’s life cycle, beginning in design and transitioning into manufacturing and field service.”

“Testing DDR3 Memory with Boundary Scan / JTAG” is available now on the ASSET web site here Other informative eBooks, white papers and videos on issues relating to chip, board and system debug, validation and test can be downloaded from our eResources