ASSET InterTech's Boundary-Scan Test, Processor-Controlled Test and I/O Instrumentation for Intel® IBIST are unique tools for access, auto­mation and analysis of embedded instrumentation.

ScanWorks® Technologies
 - Embedded Instrumentation

JTAG (IEEE 1149.x)

CPU Emulation

I/O Instrumentation

Intel® IBIST

IJTAG (IEEE 1687)

ScanWorks® Platform for Embedded Instruments

CPU Emulation

Many microprocessors have a certain number of pins devoted to what can generically be called a debug port, although many vendors have their own names for these interfaces. Intel®, for example, calls its debug port an eXtended Debug Port (XDP) while Freescale™ refers to its debug port as the Background Debug Mode (BDM). Whatever the name, the functionality is generally the same.

Chip vendors have included debug ports on their devices because they are used during development and manufacturing to debug and troubleshoot chips. In-circuit emulators also make use of these ports to substitute an emulated version of the processor for the purposes of debugging embedded software and system functionality.

For Circuit Board Validation, Test & Debug…

At the level of a functional circuit board, processor debug ports can be extended to a connector on the board. Bringing these signals to the edge of a board allows access to on-board resources for the purposes of validation, test and debug on the host circuit board as well as the system. In most cases this is advantageous since a processor is often the most powerful test and measurement instrument on many circuit boards. For example, the resources of the processor can be appropriated for various at-speed functional and structural tests. This is known as processor-controlled test (PCT).

The following are some vendor-specific examples of processor debug ports.

Intel’s XDP

When fully implemented, Intel’s eXtended Debug Port (XDP) processor debug port is a 60-pin small form-factor connector that can be used for run control of the device and platform, and, in some cases, access to some system control resources. It can also be used to access the boundary-scan (JTAG) infrastructure on the device and the circuit board.

Click here to download Intel’s “Debug Port Design Guide for UP/DP Systems”.

Click here to download Intel’s "JTAG 101 IEEE 1149.x and Software Debug" Whitepaper.

Freescale BDM

The Freescale Background Debug Mode (BDM) is typically implemented with a 10- or 26-pin connector on the circuit board. The boundary-scan (JTAG) signals can be accommodated via the BDM. As a result, the BDM port can be used to perform non-intrusive board tests (NBT) utilizing several technologies such as boundary scan and processor-controlled test.

Watch the short "PCT Overview" and "PCT Demo" movies for a rapid understanding of the benefits and features of PCT.

For a complete overview of PCT, click here.

PCT can be effectively deployed across a wide range of applications. Click on any of the following for more information.

PCT white papers and other documents are available here.

For more information on any of the other technologies supported by the ScanWorks platform, click one of the following links:

Find out how much additional coverage and insight Processor-Controlled Test will provide on your own board designs.

PRIVACY STATEMENT  |  CONTACT US  |  RESOURCES

2201 N. Central Expy., Ste 105, Richardson, TX 75080
(888) 694-6250 or (972) 437-2800
Copyright © 2001-2010 ASSET InterTech Inc. All rights reserved.