ScanWorks® Platform for Embedded Instruments

Intel® IBIST Embedded Instrumentation

In 1999, Intel Corporation began developing its Interconnect Built-In Self Test (IBIST) – an embedded instrumentation technology for placement in the company’s leading chips and chipsets. The intent of this proprietary specification was to create a standard on-chip infrastructure for validating, testing and debugging the high-speed I/O (HSIO) buses that interconnected Intel chips on circuit boards. Intel and its customers utilize IBIST extensively. ASSET’s ScanWorks platform for embedded instruments is the only toolkit supporting Intel IBIST. In fact, Intel does not provide IBIST tools; it relies upon ASSET as a strategic supplier of IBIST tools.

Intel began developing IBIST because it realized that “conventional testing methods will not be sufficient” as a result of certain technological trends in the industry.¹ Further, Intel stated: “The need for better design validation and factory test methods has driven the development of the IBIST methodology.”¹

Intel IBIST addresses both the static and high-frequency fault spectrum associated with high-performance buses. The IEEE 1149.1 JTAG/boundary scan standard and its Test Access Port (TAP) are employed for physical access to the embedded on-chip IBIST functionality.

The focus of IBIST is board-level chip-to-chip validation and testing. It can be applied to many of the buses that are typically implemented today on Intel-based platform designs, including Intel® QuickPath Interconnect (QPI), Direct Media Interface (DMI), PCI Express® (PCIe), Scalable Memory Interface (SMI), and the Double Data Rate 3rd generation (DDR3) memory bus.

IBIST functions by generating synthetic patterns and performing error checking at the receiving end of the connection between two devices. Because it inspects received bits, IBIST can empirically determine the bit error rate (BER) that is actually occurring at the physical (PHY) layer. In addition, timing and voltage offsets can be adjusted to determine the amount of operating margin that is available on a particular bus. An IBIST tool can then plot this margin data as a virtual eye diagram to visually portray the signal integrity on the bus. All IBIST validation and test routines are performed independently of a platform’s operating software and without need for any external hardware other than a JTAG interface pod.

Resources:

¹ “Intel® IBIST, the Full Vision Realized” by Jay Nejedlo and Rahul Khanna, Intel Corporation, as presented at the IEEE International Test Conference, 2009.
Click here to access the ITC web site where this paper can be purchased.
 
“Embedded Instrumentation Has Intel® Xeon® Processor 5500 Series Designs Covered” by Tim Caffee, vice president of design validation, ASSET InterTech, Embedded Intel Solutions. Click here.

YouTube video: “Testing Intel Xeon 5500 / Core i7 (Nehalem) platforms” by ASSET.

“Structural Testing of High-Speed Serial Buses: A Case Study Analysis” by Eric Johnson, ASSET InterTech, presented at the 2006 IEEE International Test Conference.

• White paper
• Slides

“Remote Test and Diagnostics Infrastructure Using IBIST” by Rahul Khanna, Mohan Kumar, Dominic Fulginiti, Jay Nejedlo, Venkat Chava, Intel Coporation.

For more information on any of the other technologies supported by the ScanWorks platform, click one of the following links:

• What is Embedded Instrumentation?
• JTAG (IEEE 1149.x)
• Processor Debug Ports
• I/O Instrumentation
• IJTAG (IEEE 1687)

Find out how Intel® IBIST can help to validate your own board designs.