ScanWorks® Platform for Embedded Instruments

Core Instrumentation

For years, chip makers have embedded certain instruments into their devices because core instrumentation is a more effective way to characterize, validate, test and debug their devices. The types of instruments manufacturers have embedded include memory built-in-self-test (BIST), logic BIST, device monitors, serdes instrumentation and others.

This approach has become a practical imperative, given the increasing complexities of semiconductors, and new and exotic 3D multi-die packaging technologies, such as system-in-package (SiP), package-in-package (PiP) and package-on-package (PoP). Of course, for some time now embedded instruments have been essential for testing system-on-a-chip (SoC) packages. In many cases, the internal nodes on 3D chips, SOCs, SiPs, PiPs and PoPs are not accessible to the bonding pad that links the chip to the trace on the circuit board. In addition, signal voltages have shrunk to extremely low levels and noise tolerances have become negligible.

Accessing and Managing Core Instruments

Several IEEE standards have been or soon will be ratified to simplify the access, automation and analysis of core instrumentation beyond the chip test and debug phase. With these standards core instruments can be employed in circuit board and system validation, and test and debug applications. Two of the most pertinent standards are IEEE 1149.7 enhanced boundary scan and IEEE P1687 Internal JTAG (IJTAG).

The IEEE 1149.7 standard builds on and enhances the original IEEE 1149.1 boundary scan standard. Certain features of IEEE 1149.7 such as its compact two-wire interface and a wider range of architectural options make it particularly well suited for applications involving the validating, testing or debugging SOCs, 3D chips, SiP, PiP and PoP packages.

Ratification of the IEEE P1687 IJTAG standard is expected in early 2011. This specification standardizes the interface to embedded core instruments and defines a methodology for access, automation and analysis of their output.

Resources:

A white paper by ASSET’s Al Couch, chief technologist for core instrumentation. “Synergy of two emerging standards will drive 3D chip and circuit board test”

Technical paper presented at the International Test Conference (ITC) by Adam Ley, ASSET’s chief technologist for boundary scan. “Doing more with less – An IEEE 1149.7 Embedded Tutorial”

Article by Chief Technologist for Core Instrumentation Al Crouch that appeared in Future Fab. “Driving 3D Chip and Circuit Board Test into High Gear”

Article by Chief Technologist for Core Instrumentation Al Crouch that appeared in ASSET’s technical e-newsletter, Connect. “Dispelling misconceptions – Two new standards deliver value with new validation and test capabilities”

For more information on any of the other technologies supported by the ScanWorks platform, click one of the following links:

• Boundary-Scan Test (JTAG)
• Processor-Controlled Test (PCT)
• I/O Instrumentation

Find out what value Core Instrumentation would provide in your own chip and board designs.