ASSET InterTech's Boundary-Scan Test, Processor-Controlled Test and I/O Instrumentation for Intel® IBIST are unique tools for access, automation and analysis of embedded instrumentation.
ASSET was a major contributor to the development of the IEEE 1149.1 Boundary-Scan Standard (JTAG) during the 1990s. Since then, the ScanWorks platform has achieved a leadership position in the market, providing equipment manufacturers with the ability to pinpoint and analyze structural defects on circuit boards during design, manufacturing and field service.
Boundary scan came about because the fine-pitch pins on chips could not be probed by test systems. In addition, the pins on some devices were disappearing under the silicon die in chip-scale packages, such as ball grid arrays (BGA). Moreover, many circuit boards could not accommodate the test pads that had been used by test systems. In contrast to test systems that rely on the physical contact of a probe, boundary-scan tests are applied to a circuit board through a connector and the four-wire interface on boundary scan’s Test Access Port (TAP). On chips, this interface is commonly referred to as the JTAG port, which comes from the informal name of the working group that began the development of the standard, the Joint Test Action Group.
When deployed in concert with other non-intrusive validation and test technologies, such as processor-controlled test (PCT), I/O instrumentation and core instrumentation, chips, boards and systems can be thoroughly and cost-effectively validated, tested and debugged.
The original IEEE 1149.1 Boundary-Scan Standard has spawned a family of structural test standards.
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