ScanWorks® Platform for Embedded Instruments

I/O Instrumentation Technologies

Validating and testing serial input/output (I/O) buses or chip-to-chip links with traditionally intrusive methods is expensive, difficult and often ineffective when the speed of thes of bus reaches five gigabits per second (Gbps) or higher. In fact, most designs prohibit the placement of test pads for intrusive probe-based validation and test methodologies on these high-speed buses because doing so would corrupt the signaling on the bus.

As a result, many chip vendors are embedding validation and test instrumentation into their chips so that high-speed I/O buses can be validated and tested non-intrusively – without probes or bed-of-nails fixtures. Generally, these embedded instruments assert test patterns onto the bus to perform a variety of tests such as bit error rate tests (BERT), margining tests and others. Deploying I/O instrumentation testing in concert with other non-intrusive technologies, such as processor-controlled test (PCT), boundary-scan test and IJTAG core instrumentation testing, results in validation and test strategies that are more thorough and cost-effective.

Some examples of I/O instrumentation, several high-speed buses that require non-intrusive validation and testing, and various testing techniques include:
Intel® IBIST
Intel ® QPI
PCI Express
DDR3 bus
Embedded BERT
Margining

Intel® IBIST

Intel IBIST (Interconnect Built-In Self Test) is an embedded instrumentation technology that Intel is inserting into its next-generation chips and chipsets. It was developed as a standard infrastructure for validating, testing and debugging high-speed I/O which could be supported by a common software toolset. Intel makes use of IBIST from the very beginning of product verification including initial power-on silicon debug. At the board level, IBIST is employed to validate signal integrity and in non-intrusive board test (NBT) applications. It is a staple throughout the back-end product validation process and is also utilized in end-customer validation and high-volume testing.

Web page: Intel IBIST Toolkit for the ScanWorks Platform

Fact Sheet: “ScanWorks Intel IBIST QPI Validation Toolkit”

Avago IBIST

ScanWorks has I/O instrumentation tools for Avago Technologies’ Intel® Quick Path Interconnect (QPI) SerDes (serializer/deserializer) core which includes Intel IBIST and is suitable for ASICs in high-performance server applications.

News Release: “ASSET’s ScanWorks supports on-chip evaluation of Avago Technologies’ ASICs”

Intel® QPI (QuickPath Interconnect)

QPI is a point-to-point high-speed link technology developed by Intel as an interconnect to shared memory. QPI was introduced with the Nehalem and Tukwila Intel microarchitectures to optimize the parallel processing performance of platforms based on these and successive generations of advanced processors. With Intel QuickPath technology, each processor features an integrated memory controller and high-speed interconnect to link to other processors and components.

PCI Express®

PCI Express (PCIe) was a high-speed serial replacement for the parallel PCI I/O interconnect bus standard which was originally developed by Intel. The first generation of PCIe doubled the data transfer rates of PCI. PCIe is a two-way, serial connection that carries data in packets along pairs of point-to-point data lanes. Initial bit rates for PCIe reached 2.5 gigatransfers per second (GT/s) per lane, which equates to data transfer rates of approximately 200MB/s. Since its introduction, PCIe has been updated several times. The most recent instantiation, PCIe Generation 3, has a speed of eight GT/s.

PLX® visionPAK

ScanWorks will support PLX® Technology’s on-chip visionPAK™ packet generator/system analyzer toolset for PCI Express switching devices.

News Release: “ASSET’s ScanWorks will support PLX Technology’s PCI Express switch family’s visionPAK diagnostic toolset”

DDR3 Memory Bus (Double Data Rate Memory Generation 3)

DDR3 is a memory interface technology that typically connects a system’s processor to its external synchronous dynamic random access memory (SDRAM) storage. The main benefit of DDR3 over previous memory interfaces is its higher bandwidth, which is made possible by DDR3's eight-burst-deep pre-fetch buffer. In contrast, DDR2's pre-fetch buffer was four bursts deep while DDR had a two-burst-deep pre-fetch buffer. DDR3’s high-speed data transfer rates can reach up to 2.133 GT/s.

Embedded BERT

Unlike external bit error rate testing (BERT) which relies on intrusive probes placed as close to a receiver as possible, non-intrusive embedded BERT takes advantage of embedded I/O instrumentation and physically measures the error rate at the actual receiver. With the help of embedded I/O instrumentation, embedded BERT is able to see what is happening at the receiver in the silicon. In contrast, external BERT is severely limited since it requires a specialized fixture and cabling, and cannot typically be tested in the normal system.

Margining

Given a set of various signaling parameters for a high-speed serial interconnect on a circuit board, margin testing measures the difference or the margin between an operating state on each parameter and the outer acceptable limit. Margin testing may involve placing stress on one or more interconnects in order to identify possible failure scenarios on the high-speed links on a board. Margin testing will be more thorough when stress can be placed on as many lanes as possible at the same time, since the operation of one lane can often affect a neighboring lane through crosstalk and noise.

For more information on any of the other technologies supported by the ScanWorks platform, click one of the following links:

• What is Embedded Instrumentation?
• JTAG (IEEE 1149.x)
• Processor Debug Ports
• Intel® IBIST
• IJTAG (IEEE 1687)

Ask us for the ROI you're likely to get when you validate and test high-speed I/O on your board designs.