CPU Emulation via JTAG/BDM Debug Port

PCT's CPU Emulation uses the JTAG port to deliver test and diagnostic code, which is run at full CPU speed. This includes bus tests, memory tests, and I/O tests. PCT takes control of the CPU at reset, preventing it from running boot code. It then instructs the CPU to write appropriate test data to each addressable device, sequentially verifying or diagnosing the device and its associated interconnects and buses.

Using CPU Emulation in addition to JTAG allows PCT to greatly extend test coverage:

• Core logic can be functionally tested in digital ICs.
• Non-boundary-scan enabled ICs can be structurally tested.
• At-speed testing of buses.
• … and much more …

JTAG / Boundary Scan Testing

PCT can run JTAG / Boundary Scan tests to verify a board's component interconnections. PCT supports vector files written in the Serial Vector Format (SVF). A description of the SVF standard is available on our website at the following address:

http://www.asset-intertech.com/support/svf.html

SVF files can be generated by most 3rd party ATPG tools. During test execution, both emualtion and boundary scan tests can be run as an automated sequence through PCT.

I/O Stimulus-Response

PCT communicates with a wide range of I/O test cards, housed in the I/O Emulation Unit’s 16 slot chassis. These cards generate input signals and measure output signals for all types of standard and custom I/O circuits. Closed loop feedback to the Test Controller Card in the host system enables PCT to compare stimulus with response. Testing is faster than when using real peripheral devices, and far better diagnostics are provided. The full I/O path is tested, right out to external connectors. Available cards include Keyboard, Mouse, IrDA, Serial, Parallel, USB, Firewire (IEEE 1394), Ethernet, SCSI, IDE, SATA, Video, LCD Checker, Audio, Modem, Battery Simulator, Analog I/O, Digital I/O, and a Prototyping Card.

The PCT Test Executive

PCT accomodates a wide range of applications, including board development, manufacturing test, manufacturing debug, and field returns debug. For example, the Interactive mode of operation is intended for board development and debug: this mode provides tools for directly modifying and reading device registers and memory locations, without having to program tests. In contrast, the fully-automated Operator mode runs pre-scripted tests, which either supply simple pass/fail results for manufacturing, or comprehensive graphical / textual guidance for board repair.

A Typical Test Sequence

Board tests are divided into sub-tests for each addressable device on the board. The tests begin at the CPU and work progressively away from the CPU. To see a sample test sequence, go to this page.

PCT Demos

To see the PCT test executive in action, either download our demo, or contact our Sales Team.