PCT system configuration

The animated diagram above shows the various configurations of PCT that are used to test and diagnose a processor-based board. The diagram is a Flash movie - if you don't see the movie, you can download the latest Flash player from this website.

All Configurations

All PCT configurations require a Test Controller Card (PCI-200EJ).

CPU Emulation Configuration

PCT connects the PCI-200EJ to the Debug Port of the UUT processor via a Processor Control POD. This POD translates generic signal levels and protocols produced by the PCI-200EJ so that they match the requirements of the specific processor. It also permits the PCI-200EJ host computer to be sited at a distance from the UUT.

CPU Emulation with full I/O Configuration

The optional I/O Emulation unit allows I/O ports to be verified right out to external connectors during PCT testing. This unit monitors and supplies feedback to I/O ports, avoiding the need to attach real devices for full functional testing of I/O ports. Programmable cards are available for the I/O Emulation unit to generate and measure analogue and digital signals. Alternatively, third party instrumentation such as DMM's and DSO's can easily be combined with a PCT solution.

JTAG (Boundary Scan) Configuration

PCT can also run SVF-format JTAG tests that have been created by 3rd party ATPGs, such as our ScanWorks® solutions. The configuration depends on the number of JTAG scan chains and headers provided on the board under test. If the CPU is part of a larger scan chain containing the other components, the same POD that is used for CPU Emulation can also execute the JTAG tests in some processor archetictures. If some components are on a second JTAG chain, an additional JTAG POD will be needed.

Test Programming

Test programming is via ASSET's test scripting language or using standard programming languages such as C, C++, National Instruments™ CVI™, or Visual Basic®. In addition, standard test executives, such as National Instruments™ TestStand™ can be easily integrated.

PCT system operation

CPU Emulation Tests

When running CPU Emulation tests, the PCT PCI-200EJ controller issues commands to the UUT's processor via its debug port. The first step in a test cycle is to stop all normal processor activity, giving the controller full control over the UUT's operation. Once in control, the processor is used as a means to test the rest of the UUT. All UUT's can be divided into a series of functional blocks e.g. USB, A/D, etc. The operation of each functional block is controlled using processor read/write cycles. By sequentially accessing all functional blocks from the processor down, the debug port can exercise, test and monitor the operation of all UUT functions. In addition, fully-automated diagnosis is possible because testing is top-down. Diagnostic messages analyze the defective block, and the cause of the defect, e.g. short on a specific line of the PCI bus, etc.

The optional I/O Emulation Unit is used to monitor and provide feedback during the testing of I/O devices. When the USB port is being tested, for example, the processor sends data to its output register, which is picked up by the I/O Emulation unit and is returned to USB input register. The processor is directed to read and compare this with the sent data, verifying the function of the port.

PCT systems are supplied with a wide range of pre-programmed test scripts (e.g. Bus, memory, USB, Infra-red, etc.) allowing rapid integration in test environments.

JTAG (Boundary Scan) Tests

PCT runs JTAG test vector files that have been generated by JTAG test solutions, such as ScanWorks®. These files must be in Serial Vector File format (SVF). The JTAG testing can be combined with CPU Emulation testing: only a sinlge board test script needs to be run to automate both test methods. The Interactive mode of running SVF files is illustrated on this page.