JTAG Testability Checklist:

2.  On-Board Devices Checklist

2.1. Identifying Boundary-Scan or JTAG Devices

Identify all IEEE 1149.1/1149.4/1149.6/1532 jtag devices

•  SoCs
•  ASICs
•  Buffers
•  Off the shelf
•  Memory
•  Microprocessors
•  DSPs
•  PLDs
•  SERDES
•  …

2.2. JTAG/Boundary-Scan Devices:  Checking BSDL Files

Check BSDL files for accuracy and correctness:

•  What tests were made on the BSDL file (syntax, semantics, hardware verification tests) and how were the tests generated? Ask the vendor.
  •  How did the vendor create the BSDL files – automatic creation or manual?
  •   What level of the Standard applies: 1990, 1993 or 2001? (Check the use statement in the BSDL file for each device)
•   Are there any known non-compliant features and are they identified? (They should be recorded in the Design Warnings section of the BSDL files. You might also want to check the data sheet.)
•   Are compliance-enable pins defined in the BSDL file? (There are examples where the compliance-enable pins exist but are not mentioned in the BSDL file.)
•   Check the need for and the presence of custom packages (“use STD_1149_1_1994.all; use company_custom_ package.all”)
•   Is the maximum frequency for TCK defined? If so, is this a default value (cut and pasted from a template) or the actual value?
•   Does the device contain an analog section? If so, check to see if any boundary-scan (JTAG) cells exist between the digital and analog sections (not mandatory for 1149.1 mixed-signal devices unless the INTEST instruction is implemented).
•   Is there an audit trail for BSDL checking if the JTAG (boundary-scan) and /or the functional logic has been updated? Do device re-spins automatically cause an update to BSDL files? (Note: if the functional logic changes, the contents of the Identification register should also be updated. Often, it is not.) How are users notified of any BSDL changes?
•   What 1149.1 synthesis program was used? Is the program robust and proven?
•   Is there a central database of known problems with BSDL files? Have you checked the database?
•   Be especially careful of DSP devices. They are notorious for containing a variety of non-compliant features.

2.3. Other Boudary-Scan Device Property Checks

•   Are there any optional public instructions - IDCODE, USERCODE, INTEST, CLAMP, HIGHZ, RUNBIST?
•  For RUNBIST, is there information on how long the self-test will run and what the expected Pas/Fail result will look like?
•   Are there any private instructions? If so, is it clear what these instructions do? Can they be used at prototype-board debug? (Be careful. BSDL files contain only the minimum information about the behaviour of private instructions. Use private instructions with care.)
•   Does the device have the optional TRST* signal? If there is no TRST* pin, the device should automatically power-up in the Test-Logic Reset state. Does it do this?
•   What happens if two or more active outputs driving complementary logic values are shorted for any length of time? Is the resulting sort-circuit current limited or can one active output drive against another active output and cause damage? If so, it is possible for damage to occur during interconnect test.
•   What are the power-up states of three-state outputs (they should be high-Z) and bidirectional signal pins (they should be inputs)? Note: this should happen in normal functional mode.
•   Can the status of three-state and bi-directs be controlled through JTAG cells or directly from the edge connector or via physical nails from an ICT or FPT tester?
•   Has the device been certified to be ground-bounce free when in worst-case EXTEST mode? (There should be no 1149.1-induced ground-bounce inside the device.)
•   At the physical level, are TAP pins placed physically next to each other or are they well-separated or positioned close to Not Connected (NC) pins? (They should be well separated or close to NC pins. Shorts between TDI and TDO can cause diagnostic problems.)
•   Are there any LVDS outputs or inputs? If so, are there boundary-scan (JTAG) cells on these pins and where are they placed? (See also section 3.17)

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