JTAG Testability Checklist:

1.2. Tester Availability and Tool Selection

What mix of tester types is available?

•  Boundary scan or JTAG devices on board?
•  ICT: In-Circuit Test (multi-nail, fixed location)?
•  FPT: Flying Probe Test (few nails, movable location)?
•  AXI: Automated X-ray Inspection?
•  AOI: Automated Optical Inspection?
•  Emulation Test?

Tool selection

•  Does this design have any special features that should be considered when tools are selected?
•  Has a volume manufacturing test strategy been specified that could benefit from re-use of tests created during prototype debug?
•  Do the tools used for emulation, test, and In-System Configuration (ISC) support the scan path  management device used?

1.3. Checking Board Power-Up Sequence

Check the board power-up sequence

•  Does the board require a special power-up sequence e.g. different power-supply voltages applied in a certain sequence, or based on first loading a boot ROM? If so, is the sequence documented?
•  Does the board contain a master reset signal? Does this signal place all on-board devices into a known initialized safe state?
•  Are there any un-programmed PLDs or un-configured FPGAs on the board? If so, do these devices power-up in a safe state? And do devices that have access to un-programmed PLDs also power-up in a safe state?
•  Do boundary-scan devices power-up in the Test-Logic Reset state? (They should do if there is no TRST* signal but 1149.1 synthesis EDA vendors do not always comply with this requirement.)

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