JTAG Testability Checklist :

Chip & Board Testability Assessment Checklist

Prepared by
Ben Bennetts, DFT Consultant
for ASSET InterTech, Inc.

1 July 2005

Abstract:

This document summarizes a checklist of questions to assist testability assessment of a board mostly from a boundary-scan perspective but also from other test perspectives (ICT, FPT, AXI, AOI). The checklist is based on a set of Chip and Board Testability Guidelines, available from the author, also available on ASSET InterTech’s web site, www.asset-intertech.com.

1.  Before You Start

1.1.  Data Requirements 

Before you start, you will need:

•  Board level netlist
•  BSDL files for all IEEE 1149.1 devices and, if present, 1149.4, 1149.6 and 1532 devices
•  Cluster model files, also known as characteristic model files, containing IO and functional data for all non-boundary-scan devices
•  Board schematic
•  Data sheets for the devices on the board
•  Bill Of Materials (BOM)
•  A board

Previous : Next