ENTITY SN74BCT8374
PROCESS BadIRVerify IS

-- Prolog for this program:
sc_reset; -- Reset the UUT
sc_clear; -- Clear all Expected buffers to don't-cares
sc_setCompareMode (TRUE); -- Enable automatic comparisons

-- This program intentionally checks for the wrong two LSBs
-- in the Instruction register to demonstrate sc_failed.

Instruction.Expected[1,0] := '11'B;
Instruction.TDI := BYPASS;
sc_scan (IR);

IF sc_failed = SC_PASS THEN

-- This code won't execute unless the device isn't working.
put data ('The Instruction register LSBs are 11', newLine);

ELSIF sc_failed = SC_FAIL THEN

-- This code should be executed.
put data ('The Instruction register LSBs are NOT 11',
newLine);

ELSE

-- This code won't be executed unless the procedure
-- sc_setCompareMode(FALSE) is called earlier.
put data ('No comparison was performed.', newLine);

END IF;

END PROCESS;