ScanWorks® JTAG Test Development Station Bundle

Optional Products

Flash Memory Program Generation

On-board flash memory can be programmed with the addition of an optional feature to a ScanWorks Test Development Station. The flash memory feature takes netlist information and flash memory models and automatically detects the boundary-scan signals that program flash devices. Then, programming operations are generated to read and write to flash memory. For detailed information refer to the Flash Memory Programming Fact Sheet on the ASSET website.

IEEE 1149.6 High-Speed Interface Testing

The optional IEEE 1149.6 High-Speed Interface Testing feature adds the ability to test AC-coupled connections between devices. Many new designs are using high-speed serial interfaces for data transfer between devices and boards. In many cases these connections include coupling capacitors to compensate for electrical noise or logic level mismatches. The IEEE 1149.6 standard was developed to provide a method for testing through these coupling capacitors with boundary scan. Specialized boundary-scan cells are built into IEEE 1149.6-compliant devices that enable logic levels to be transferred from device to device at the speed of the interconnect net. To implement 1149.6 tests, ScanWorks automatically identifies the nets that can be tested and creates interconnect tests for them, adding test coverage for nets that may have been untestable by any other means.

IEEE 1532 Concurrent In-System Configuration

The optional IEEE 1532 Concurrent In-System Configuration feature simultaneously loads configuration data into multiple PLDs from different vendors, significantly reducing overall PLD configuration time. In most cases the total programming time for multiple devices is approximately the time it takes to load the slowest device.

IEEE 1532 In-System Configuration for Programmable Devices standard specifies a method for loading configuration data into PLDs after they have been assembled on a board. It defines an internal register structure that is accessible by boundary scan and described by standard BSDL files. It also defines BSDL syntax to describe the device-specific programming algorithms, and a data file format that is read by the programming tools which program, erase, verify and perform other operations of PLDs.

The IEEE 1532 BSDL files are provided by PLD device vendors while the IEEE 1532 programming data files are created by the PLD vendor tools. As a result, ScanWorks does not need to offer special support for every new PLD device. New devices are supported as soon as they are available and supported by vendor tools. In the ScanWorks IEEE 1532 action, the devices to be programmed concurrently are selected from a list of IEEE 1532-compliant devices in the design. For each device, the programming tasks that will be performed are selected from a list of available operations. You can also choose if the selected devices are to be programmed concurrently or sequentially.

IEEE 1532 Concurrent In-System Configuration is supported in ScanWorks by the ispVM™ software from Lattice Semiconductor. This proven technology provides the best solution in the industry.

The devices listed in Table 1 are supported in ScanWorks. (Note: Xilinx XC9500, XC9500XL and XC9500XV are compliant with IEEE 1532 but not yet supported in ScanWorks.)

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