ScanWorks^® JTAG Memory Access Verification

Memory Device Models

Models of memory devices are provided to ease the test generation process. The models contain the read/write protocols and the package pin information necessary to automatically determine boundary-scan access to the device and to create the scan vectors needed to test interconnect to the memory cluster. The read/write protocols pin and package information are accessible to allow the user to adjust an existing model to work with similar devices.

Test Operations

The Memory access verification action provides several levels of tests operations, enabling you to optimize the action for speed of application or for diagnostic information. You can also test the target memory cluster memory cells. Interconnects are tested quickly with the Wagner counter patterns while more complete diagnostics can be obtained by using walking patterns. Special tests to diagnose some control signal defects are also provided, as well as vectors to be used to interactively debug defective boards. The cell test operation writes to and reads from every memory location with in the specified range and reports locations that fail.

Interactive Memory Access

The memory access verification action provides interactive access to the target memory cluster. The test access window enables you to run the generated tests and view their application on a scan-by-scan basis or a read/write cycle basis. This provides a very flexible means of verifying correct memory access protocols and of debugging defects detected during board test. You can also write to and read from specific memory location interactively.

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