ScanWorks^® JTAG Interconnect Repair Station Bundle

Diagnostics

Interconnect Test Diagnostics

The diagnostic tools of the Interconnect Repair Station will generate diagnostic reports to the level of a net or pin. Moreover, the station features a built-in interactive debug tool. The diagnostic tool reports all information about any net where an unexpected response is detected, including the most likely type of defect (open or shorted), and the device and pin information about all other connections to the net.

The built-in interactive debug tool provides a state table view of the interconnect test results. Each scan operation is shown for selected pins or nets so you can see exactly what conditions lead to miscompares. Miscompares are highlighted and the driving pins are clearly indicated. You can rerun the tests from within the debugger and also observe specific pins or set them to specific logic levels.

Memory Access Verification Diagnostics

Tests created with ScanWorks’ Memory Access Verification tool detect defects on the data, address and control signals linking boundary-scan devices and non-boundary-scan memory devices. Defects can be diagnosed down to the level of a data or address signal, and, in some cases, to a specific control signal. A diagnostic report indicates the signal and specific memory pin involved. Pins with defects are linked to the board layout view in the optional Graphical Fault Highlighting tool, making it easy for you to locate the suspected pin on the board being tested.

Like the interconnect debugger, an interactive debugger compiles a state table view of the scan operations executed during the read/write operations that made up the test. Data is displayed in two modes: cycle mode that shows only the significant scans and vector mode that shows every scan.

Macro Language

The Interconnect Repair Station’s macro programming language is a powerful, high-level language that provides access to the design at any level; from individual scan cells to entire test registers or subsets of test registers. With specialized functions and procedures you can control or observe a specific pin or create a complete test for a cluster of non-boundary-scan logic. Macro programs can establish “safe” conditions before a boundary-scan test is applied to the board or the safe state can be maintained throughout testing.

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