JTAG Guidelines for Board DFT - Part 2: 

If the board contains programmable devices, such as CPLDs or FPGAs, make sure that the devices can be programmed, and re-programmed, from a boundary-scan/JTAG interface – see next slide. Ideally, such devices should be compliant to the new IEEE 1532 - 2002 In-System Configuration Standard.

All significant control signals that control the operational status of on-board devices must be directly controllable when the board is in test mode. This includes board Power-On Self Test, Boot or Program signals e.g. Power-Down, Init, Reset, PRGM_, BOOT_.

Xilinx xc2s200: an example of a programmable device that has compliance pins to establish the 1149.1 logic. The two pins, PROGRAM and PWDNB, must both be held at logic-1 to establish the boundary-scan logic.

Do not place control of compliance-enable pins downstream of the programmable device. If you do this, the chain cannot be established – a classic chicken and egg problem. One solution is an automatic power-up reset circuit on the board that has control of the compliance-enable pins. Another solution is to place the programmable device downstream of the controlling device. (Note, this will not work if there is a defect that prevents the upstream devices from being correctly chained – see below.)

Better still is to provide independent control of the compliance-enable signal e.g. through a physical nail or external connection: not through an unused boundary-scan cell.

Beware also the “blind apply” e.g. if the scan-chain order of the devices above are switched to 1-to-3-to-2, then it can be argued that the upstream path 1-to-3 can be set up and used to control the compliance-enable pins of the downstream device 2. This is true but assumes that there is no problem with the 1-to-3 path plus there is no problem with unknown values being presented to device 2’s compliance-enable pins during the initial set-up phase. It is much better to allow direct control on the compliance-enable pins.

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