JTAG Guidelines for Board DFT - Part 2:

Boundary-scan/JTAG devices that do not participate in cluster testing should be placed into known safe states. One way to do this is to hold them in a test state rather than a functional state. The CLAMP, HIGHZ and EXTEST instructions can all be used to achieve this objective.

A boundary-scan (JTAG) interface can be used to test the presence, orientation and bonding of on-board RAM devices. The tests require JTAG (boundary-scan) access to the Data, Address and Control lines of the RAMs. Commercial PC-based test systems support this use of boundary-scan (JTAG) registers.

In the case of RAM devices that are not accessible from JTAG/boundary-scan devices, 1149.1-compliant buffer devices can be used to restore JTAG access. National Semiconductor and Texas Instruments make 1149.1-compliant buffer devices for use on board internal busses e.g. the TI Octal and WidebusTM devices. It is preferable to use these devices for buffering bus signals rather than non-BS buffer devices. In the case of the TI devices, the boundary-scan registers can be set up to become a pseudo-random pattern generator (output scan cells) and CRC data compactor (input scan cells). A typical example of such a device is the SN74LVTH18502A WidebusTM Universal Bus Transceiver.

Details of all these devices can be found on the vendor’s web sites – see the “To Probe Further …” slide.

Here we see that the WE and RE control signals have been brought out to an edge-connector position to allow programmable IO pins (from the tester) to provide the control signals. This considerably reduces the time it takes to check the presence, orientation and bonding of the memory device.

If you do this, make sure that there is no damage caused by back-driving to the output drivers of the normal source of the control signals. If there is the potential for damage, design the WE and RE sources to be tristate sources and place in high-Z state during the test mode, as shown.

In-System Configuration (ISC), or In-System Programming (ISP) as it is often known, has become a major new application of 1149.1 boundary scan or JTAG. Basically, ISC is the ability to load configuration data into a Complex Programmable Logic Device (CPLD), Field-Programmable Gate Array (FPGA) or even a Flash device whilst such devices are mounted on a board.

The benefits of ISC are numerous:

• simplifies inventory management,
• reduces or removes the need for off-line programming stations,
• enables rapid prototype configuration and re-configuration, thereby increasing design flexibility,
• removes the need for on-board sockets which are often a cause of pin damage,
• reduces risk of damage caused by mechanical handling and electro-static discharge leading to improved quality of parts,
• allows just-in-time programming (also known as design for postponement) and last-minute changes e.g. choice of language, personal details (SIMM cards), et cetera
• and allows program upgrades for System and Field-Service debug.

The programming of the CPLD device is carried out via the board-level JTAG (boundary scan) access path – that is, from the edge-connector through surrounding devices to the programmable device. Surrounding JTAG/boundary scan (and non-boundary-scan) devices must be placed in a safe state so as not to interfere with the in-system programming process. Boundary-scan/JTAG devices are first preloaded with safe values (using the PRELOAD instruction) and then placed in Bypass register mode using either the HIGHZ or CLAMP instruction. Placing surrounding JTAG devices in bypass register mode also facilitates rapid access to the programmable device.

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