JTAG Guidelines for Board DFT - Part 2:

BOARD-LEVEL DFT GUIDELINES – PART 2:

On most modern boards, the only non-boundary-scan devices are simple line drivers (buffers), with or without inversion, or re-routing devices such as multiplexers. These devices are generally known as “pass thru” devices. It is a simple matter to generate Presence, Orientation and Bonding tests for such devices and then apply the tests via the embracing JTAG or boundary-scan devices.

But, on older boards, there may be non-boundary-scan MSI devices i.e. devices with more complex functions, such as flip-flops, counters, shift registers, etc. The next slide discusses how to handle such devices.

Testing non-BS MSI devices for opens and shorts via a JTAG (boundary-scan) interface (cluster testing) may not achieve 100% stuck-at and 2-net short fault coverage. Patterns for the non-boundary-scan clusters can be taken from the extensive libraries of In-Circuit Testers and validated via a fault simulator.

To maximize fault-coverage on non-BS MSI devices, ensure maximum access to their pins either via boundary-scan or JTAG registers or direct from the primary connection to the board, or by using real nails (from a flying probe or bed-of-nails fixture).

If the board is to be tested using a mix of real nails (from a flying probe or bed-of-nail fixture) and virtual nails (from JTAG/boundary-scan cells), choose the selection of the real nail access nets carefully i.e. where they will contribute the most to additional fault coverage – see Part 2 of this series. Some vendors have access-analysis tools to assist in the selection process. Note: the selection process will also impact physical layout, causing certain nets to be brought to the surface of the board for physical probe purpose.

Where possible, provide direct access to key control signals on non-BS devices so that they can easily be configured into the correct state during test. If direct control is not possible, provide indirect control from an unused boundary-scan cell.

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